TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 132

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY TXC-06312B-MB, Ed. 2
June 2005
PHAST-12N Device
DATA SHEET
TXC-06312B
(see
ParityEven
12.2 ADD BUS INTERFACE
Table
1
1
12.1.2 Drop Bus Delay
12.1.3 Drop Bus High Impedance
80)
With control field TimingDelay, see
section, an additional delay of 0 up to 15 extra CBDPCLK clock cycles can be inserted
between the Drop bus data/parity and the Drop bus timing signals, CBDPJ0J1 and
CBDPSPE. All Drop bus outputs are delayed one clock cycle when control field TimingDelay
is set to 1.
The Drop Telecom Bus interface can tristate each type of container it carries:
- AUG-1: The data and parity corresponding to an AUG-1 can be forced into a high
impedance state by setting control field AUG1_HighZ_Config (see
Maps and Bit
1 #1). Each AUG-1 can be configured independently. When an AUG-1 is not tristated all its
subcontainers (AU-4, AU-3) are also automatically out of tristate. In concatenated mode (e.g.,
VC4-4c, VC4-2c), the AUG1 HighZ configuration for the master AUG1 is copied to the slave
AUG1’s. This is done to avoid user errors in the configuration, which would result in useless
behaviour since, e.g., a VC4-4c with half it’s timeslots in tristate wouldn’t make sense.
- AU-4/STS-3c: For this type of container, also the AUG1_HighZ_Config (see above) must
be used.
- AU-3/STS-1: When operating in AU-3/STS-1 mode, the data and parity corresponding to
individual AU-3/STS-1 can be forced into a high impedance state by setting register
VC3_TUG3_HighZ (see
field is indirect accessible meaning that the control field Config_Channel (see
Memory Maps and Bit
indicate the desired AU-3/STS-1 timeslot.
The Add bus consists of the following leads:
The timing information can be input or output:
ParityIncludesTiming
• Input data CBADD(7-0)
• Input parity CBADPAR
• Input/Output clock CBADCLK
• Input/Output J0, J1, and optional V1 marker pulses CBADJ0J1
• Input/Output payload indication CBADSPE
(see
Table
0
1
Descriptions) to high for the particular AUG-1. (4 bits, LSB corresponds to AUG-
80)
Descriptions) inside the same Drop Telecom Bus must also be set to
Table 79
Even parity is calculated for the data output leads CBDPD(7-0).
Even parity is calculated for the data and timing output leads,
CBDPD(7-0), CBDPJ0J1 and CBDPSPE.
-
Telecom Bus
of the
Table 80
Memory Maps and Bit
-
Drop Bus Parity Selection
of the
Memory Maps and Bit Descriptions
Descriptions) to 1. This control
Table 81
of the
Table 80
1 3 2 o f 2 0 2
Memory
of the