TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 133

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1 3 3 o f 2 02
Output_SelectNegativeClockEdge
Sample_SelectNegativeClockEdge
Lead CBADT
High
Low
12.2.1 Add Bus Timing Modes
12.2.2 Add Bus Parity Selection
(see
(see
J0 and J1 marker pulses are always expected on the CBADJ0J1 lead. A V1 pulse is expected
when the SDH/SONET traffic contains lower-order (see
The most significant bit (MSB) of the output data is assigned to CBADD7. The MSB is defined
as the first bit received in a SDH/SONET byte. The bus rate is 77.76 MHz.
The CBADCLK clock edge on which the data (and optionally timing) signals are clocked in
can be selected.
The active CBADCLK clock edge on which the timing signals are clocked out can be
selected.
The CBADT lead selects the Master (timing signals are output) or Slave (timing signals are
input) timing mode on the Add bus interface.
The parity selection for the Add bus is according to the following table. The calculated parity
is compared to the value of the CBADPAR input lead. A parity error is indicated by the
ParityError alarm, see
PHAST-12N.
Table
Table
0
1
0
1
Master Timing Mode:
The Add bus timing leads, CBADCLK, CBADJ0J1, and CBADSPE, are Outputs. Refer
to
Slave Timing Mode:
The Add bus timing leads, CBADCLK, CBADJ0J1, and CBADSPE, are Inputs. Refer to
Figure
70)
70)
Figure
6.
7.
Output signals are clocked out on positive CBADCLK clock edge.
Output signals are clocked out on negative CBADCLK clock edge.
Table
Input signals are sampled on positive CBADCLK clock edge.
Input signals are sampled on negative CBADCLK clock edge.
- Telecom Bus -
68. Other than an alarm indication, no action is taken by the
Add Bus Timing Mode
Active CBADCLK clock edge
Active CBADCLK clock edge
“SDH/SONET Mapping” on page
PRELIMINARY TXC-06312B-MB, Ed. 2
PHAST-12N Device
DATA SHEET
TXC-06312B
June 2005
85).