TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 134

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY TXC-06312B-MB, Ed. 2
June 2005
PHAST-12N Device
DATA SHEET
TXC-06312B
(see
ParityEven
12.3 BER SUPERVISION FOR B2/B3
Table
0
0
1
1
12.2.3 Add Bus Delay
12.3.1 Bursty Distribution of Errors
70)
With control field TimingDelay, see
section, an additional delay of 0 up to 15 extra CBADCLK clock cycles can be inserted
between the Add bus timing signals, CBADJ0J1 and CBADSPE, and the Add bus data/parity.
All Add bus inputs are delayed one clock cycle when control field TimingDelay is set to 1, for
all timing modes.
The PHAST-12N supports detection of the degraded signal (dDEG) and the excessive error
(dEXC) defects for both line (B2 BIP-96 in STM-4/OC-12 mode, B2 BIP-24 in STM-1/OC-3
mode) and path (B3 BIP-8).
The assumed distribution of errors needs to be configured:
If a bursty distribution of errors is assumed, the excessive error defect is assumed to be false.
The degraded signal defect detection is based on one second performance monitoring block
error count.
Two sets of configuration registers are provided: one for setting the defect, one for clearing (to
allow some hysteresis).
The degraded signal defect (dDEG) is declared if DEG_DetectionWindowSize consecutive
bad intervals are detected - an interval is the one second period used for performance
monitoring. For B2 (MSOH) an interval is declared bad if the number of errored blocks in that
interval is greater than or equal to DEG_DetectionErrorThreshold. For B3 (POH) an interval
is declared bad if the number of errored blocks in that interval is greater than
DEG_DetectionErrorThreshold. Remark the slight difference between the B2 (MSOH) and
B3 (POH) detectors configuration!
PoissonErrorCheck
ParityIncludesTiming
(see
0 (Default)
1
Table
0
1
0
1
70)
Bursty distribution of errors is assumed (SDH).
Poisson distribution of errors is assumed (SONET).
Odd parity is calculated for the data input leads CBADD(7-0).
Odd parity is calculated for the data and timing input leads,
CBADD(7-0), CBADJ0J1 and CBADSPE (CBADT is high).
Even parity is calculated for the data input leads CBADD(7-0).
Even parity is calculated for the data and timing input leads,
CBADD(7-0), CBADJ0J1 and CBADSPE (CBADT is high).
-
Telecom Bus
Table 70
-
Drop Bus Parity Selection
of the
Description
Memory Maps and Bit Descriptions
1 3 4 o f 2 0 2