TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 54

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY TXC-06312B-MB, Ed. 2
June 2005
PHAST-12N Device
DATA SHEET
TXC-06312B
Notes:
1. The optional V1 pulse only occurs during the first frame of the low order multi-frame as indicated by the H4 byte. It is
2. The active CBDPCLK clock edge on which the data/parity and timing signals are clocked out can be selected, see
3. An additional delay of 0 up to 15 extra CBDPCLK clock cycles can be inserted between the Drop bus data/parity and
always located twelve clock cycles after the corresponding J1 pulse.
“Drop Bus Interface” on page
the Drop bus timing signals, CBDPJ0J1 and CBDPSPE, see
correspond to a delay of 0 clock cycles.
CBDPCLK clock period
CBDPCLK duty cycle
CBDPD(7-0)/CBDPPAR/CBDPC0J1/CBDPSPE out
valid delay from DCLK
CBDPD(7-0)/
CBDPJ0J1
CBDPCLK
CBDPSPE
CBDPPAR
(Output)
(Output)
(Output)
(Output)
Detailed timing diagrams for the PHAST-12N device are illustrated in
26
are measured with a maximum load capacitance of 50 pF unless otherwise stated. Timing
parameters are measured at the voltage levels of (V
V
50 pF Load
IL
)/2 for input signals.
with values of the timing parameters tabulated below each waveform diagram. All outputs
C1/J0 pulse
t
Parameter
CYC
131. The waveforms shown correspond to the positive clock edge selection.
t
PWH
Figure 5. DROP Bus Timing
-
Timing Characteristics
9.0 T
J1 pulse #1
J1 #1
IMING
Symbol
t
D
“Drop Bus Delay” on page
t
t
PWH
CYC
t
D
-
J1 pulse #2
OH
C
Min
40
1
+V
HARACTERISTICS
OL
)/2 for output signals and (V
12.86
J1 pulse #12
Typ
50
132. The waveforms shown
Figure 5
V1 pulse #1
Max
60
6
through
V1 pulse #2
%t
Unit
ns
ns
5 4 o f 2 0 2
CYC
Figure
IH
+