TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 92

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY TXC-06312B-MB, Ed. 2
June 2005
PHAST-12N Device
DATA SHEET
TXC-06312B
10.4 POWERUP, INITIALIZATION AND STARTUP
10.4.1 Powerup of the CDR/CS
After powerup and external reset of the device, no internal clocks are active. This section
describes the way the necessary clocks need to be brought up and the initialization of the
device.
The first clock present in the device is the external microprocessor clock. The registers which
are needed to bring up the internal clocks are located in the clock domain from this external
microprocessor clock.
The clock domains which must be brought up next are:
In case the Add Telecombus is operating in Slave Mode, this is an external clock domain. The
external clock must be running in order to access the registers in this domain. If the Add
Telecombus is in Master Mode, this is a part of the System Clock domain.
At this stage of the process, the hardware interrupt can be enabled through the HINTEN field
(see
properly disabled here.
It is advised to unmask the Global Control Interrupt now. In the Global Control block, the Loss
of System Clock and Loss of Clock for the active lines must be unmasked to enable the
hardware interrupt for events on the Loss of Clock detection.
After this, the Clock Recovery/Clock Synthesis block must be configured and powered up
(see section
lasers, those must also be powered up.
It is recommended to leave RESETH (see
deasserted, the device will start a reset sequence for all of its internal RAMs. The
RamResetDone record in the Global Control block (see
domains have finished resetting their RAMs.
Once all the necessary clock domains are powered up, and the corresponding RAMs are
reset, the device will not yet be operational. Operation is halted so the device can be
configured in a clean way. Once the configuration is done, DeviceInitialized field in Global
Control can be set to 1 and the device will start its normal operation.
A startup sequence for the Clock and Data Recovery / Clock Synthesis part of the PHAST-
12N is given below (all registers can be found in the CDR/CS section of the Memory Map):
•
•
• System Clock
• Rx Line 1 Clock
• Rx Line 2 Clock
• Rx Line 3 Clock
• Rx Line 4 Clock
• Rx APS Clock
Set device in software reset: Write 0x91 to RESETH (Address 0x00A0). Other clock
domains can also be set in reset now (See Memory Map).
Write 0x0000 to IndirectAccessMode (Address 0x3A26), followed by writing 0x0017 to
IndiretAccessData (Address 0x3A5E)
Table 7
Powerup of the
of
Memory Maps and Bit Descriptions
CDR/CS). If the General Purpose Outputs are used to control the
-
Operation
-
Table
6) asserted until this point. Once RESETH is
section). The interrupt masks must be
Table
2) indicates which clock
9 2 o f 2 0 2