TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 151

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1 5 1 o f 2 02
0x001A 15 - 0
0x001C 0
0x001E 15 - 0
0x002C 0
0x0000
0x0010 0
0x0012 0
0x0014 0
0x0016 8 - 0
0x0018 0
0x0020 15 - 0
0x0024 15 - 0
0x0028 0
0x0030 3 - 0
0x0034 3 - 0
Offset
13.2 GLOBAL CONTROL
Bits
Reserved
Reserved
LastAddress
DeviceIdentification
STM4_Mode
TimeOutCount
AckOnTimeOut
CBADT
LocDivider
LocEntryThreshold
LocExitThreshold
External1secRef_Select
DeviceInitialized
GP_Input
GP_Output
Name
Table 2: Global Control
- Memory Maps and Bit Descriptions -
0x1FF rw
Init
0x20 rw
0x0 rw
0x1 rw
0x1 rw
0x1 rw
0x0 ro
0x0 ro
0x4 rw
0x2 rw
0x0 rw
0x0 rw
0x0 ro
0x0 rw
ro
Access
T_DeviceIdentification
Device identification.
STM-4/OC-12 Mode when 0x1: line 1 is a 622.08 Mbit/s signal,
lines 2 to 4 are not used. STM-1/OC-3 Mode when 0x0: lines 1
to 4 are 155.52 Mbit/s signals.
Reserved.
Reserved.
Range 0 to 511
Acknowledge Time Out Count. Specifies the Time Out after
which an Acknowledge is generated if a request hasn’t been
acknowledged. Timebase is the microprocessor clock period
(MPCLK).
Acknowledge on Time Out. An Acknowledge will be generated
upon failed accesses after a period specified by TimeOutCount
when 0x1. No Acknowledge will be generated upon failed
accesses when 0x0.
Last Address. Indicates the address of the last timed-out
request.
Note: the address returned is a word address.
Add Combus Timing Slave. Indicates the value on the CBADT
input pad (this pad configures the Add Telecombus in master or
slave mode).
Range 0 to 65535
Loss Of Clock Divider. The clock to be monitored is divided by
this number + 1 for LOC detection.
Loss Of Clock Entry Threshold. Specifies the time without
divided clock transition before declaring LOC. Timebase is the
microprocessor clock period (MPCLK).
Range 1 to 65535
Loss Of Clock Exit Threshold. LOC is deasserted when this
many divided clock transitions were detected. Detection occurs
in the microprocessor clock domain (MPCLK).
External One Second Reference Select.
The one second reference on the REFONESECCLK is used
when 0x1. The one second reference is generated internally
when 0x0.
The device processes incoming data when this value is set to
0x1. The software must set this value to 0x1 as soon as it has
finished the configuration of the device.
General purpose input (GPIN4..GPIN1).
General purpose output (GPOUT4..GPOUT1).
Range 1 to 65535
(T_GLOBAL_CONTROL)
(See page
PRELIMINARY TXC-06312B-MB, Ed. 2
Description
PHAST-12N Device
152)
DATA SHEET
TXC-06312B
June 2005