TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 186

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY TXC-06312B-MB, Ed. 2
June 2005
PHAST-12N Device
DATA SHEET
TXC-06312B
Offset
Offset
0x000C 0
0x001A 7 - 0
0x001C 7 - 0
0x001E 7 - 0
0x002A 7 - 0
0x002C 7 - 0
0x002E 7 - 0
0x0000 0
0x0000 0
0x0004 1 - 0
0x0008 0
0x0010 7 - 0
0x0012 5 - 0
0x0014 7 - 0
0x0016 7 - 0
0x0018 7 - 0
0x0020 7 - 0
0x0022 7 - 0
0x0024 7 - 0
0x0026 7 - 0
0x0028 7 - 0
0x0030 7 - 0
0x0032 0
0x0034 1 - 0
13.18 JTAG MASTER
1
2
Bits
Bits
Table 76: Path Ring Port/Alarm Interface Path Configuration
SelectExternalSource
ResetVC
ExtendRDI
TDI_TMS_bit
TCK_bit
TDO_bit
TCK_DIVIDER
Counter
TDI_Fifo_B0
TDI_Fifo_B1
TDI_Fifo_B2
TDI_Fifo_B3
TDI_Fifo_B4
TMS_Fifo_B0
TMS_Fifo_B1
TMS_Fifo_B2
TMS_Fifo_B3
TMS_Fifo_B4
TDO_Fifo_B0
TDO_Fifo_B1
TDO_Fifo_B2
TDO_Fifo_B3
TDO_Fifo_B4
Start
Done
Bit_wise_control
Name
Name
-
Table 77: JTAG Master
Memory Maps and Bit Descriptions
Init
Init
0x0 rw
0x0 rw
0x0 rw
0x0 ro
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 ro
0x0 ro
0x0 ro
0x0 ro
0x0 ro
0x0 rw
0x0 ro
0x0 Extends RDI for 20 frames when 0x1.
0x0 Select external ring port when 0x1. Internal ring port is used when
0x0 Resets an entire VC information when 0x1.
Access
0x0.
(T_JTAG_MASTER)
This bit selects if direct microprocessor control bits will be
used, instead of the FIFO’s.
The microprocessor driven TDI and TMS bit values (bit 0 =
TMS, bit 1 = TDI).
The microprocessor driven TCK clock bit value.
The microprocessor read TDO bit value.
A clock divider number to create an appropriate 10 MHz
TCK clock using the current System Clock.
6-bit shift count register.
FIFO containing TDI data to send to TAP (byte 0).
FIFO containing TDI data to send to TAP (byte 1).
FIFO containing TDI data to send to TAP (byte 2).
FIFO containing TDI data to send to TAP (byte 3).
FIFO containing TDI data to send to TAP (byte 4).
FIFO containing TMS data to send to TAP (byte 0).
FIFO containing TMS data to send to TAP (byte 1).
FIFO containing TMS data to send to TAP (byte 2).
FIFO containing TMS data to send to TAP (byte 3).
FIFO containing TMS data to send to TAP (byte 4).
FIFO containing TDO data received from the TAP (byte 0).
FIFO containing TDO data received from the TAP (byte 1).
FIFO containing TDO data received from the TAP (byte 2).
FIFO containing TDO data received from the TAP (byte 3).
FIFO containing TDO data received from the TAP (byte 4).
Start bit. Is set to trigger a transfer between microprocessor
& TAP. This bit clears the Done and Error bits.
When the transfer is completed, these bits are set:
• bit 0 = ‘Done’
• bit 1 = ‘Error’
-
Description
(T_HOPR_VC_Config)
Description
1 8 6 o f 2 0 2