TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 55

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Notes:
1. The optional V1 pulse only occurs during the first frame of the low order multi-frame as indicated by the H4 byte. It is
2. The CBADCLK clock edge on which the data/parity and timing signals are clocked in can be selected, see
3.
5 5 o f 2 0 2
CBADCLK clock period
CBADCLK duty cycle
CBADJ0J1/CBADSPE/CBADD(7-0)/CBADPAR setup time to
CBADCLK
CBADJ0J1/CBADSPE/CBADD(7-0)/CBADPAR hold time
after CBADCLK
always located twelve clock cycles after the corresponding J1 pulse.
Interface” on page
An additional delay of 0 up to 15 extra CBADCLK clock cycles can be inserted between the Add bus timing
signals, CBADJ0J1 and CBADSPE, and the Add bus data/parity,
waveforms shown correspond to a delay of 0 clock cycles.
CBADD(7-0)/
CBADJ0J1
CBADSPE
CBADPAR
CBADCLK
(Input)
(Input)
(Input)
(Input)
Figure 6. Add Bus Timing (ADD Slave Mode: Timing Signals Are Inputs)
50 pF Load
132. The waveforms shown correspond to the positive clock edge selection.
t
CYC
C1/J0 pulse
Parameter
t
PWH
- Timing Characteristics -
J1 pulse #1
t
J1 #1
S
J1 pulse #2
Symbol
t
t
t
PWH
CYC
H
t
t
H
S
see
“Add Bus Delay” on page
Min
PRELIMINARY TXC-06312B-MB, Ed. 2
40
3
0
J1 pulse #12
PHAST-12N Device
12.86
Typ
50
V1 pulse #1
Max
DATA SHEET
60
TXC-06312B
V1 pulse #2
“Add Bus
134. The
June 2005
%t
Unit
ns
ns
ns
CYC