TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 26

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY TXC-06312B-MB, Ed. 2
June 2005
PHAST-12N Device
DATA SHEET
TXC-06312B
APSTXDATAP
APSTXDATAN
REFTXCLK1
REFTXCLK2P
REFTXCLK2N
REFRXCLK
Symbol
Symbol
TRANSMIT APS PORT
CLOCK/TIMING INTERFACE
Lead No.
Lead No.
AA20
AB9
AB8
W8
AA7
AB6
I/O/P
I/O/P
I
I
I
O
LVPECL Transmit Reference Clock #2: Reference clock for the
LVTTL Transmit Reference Clock #1: Reference clock for the
LVTTL Receive Reference Clock: Optional Reference clock for
Type
-
LVDS
Type
Lead Descriptions
transmit clock synthesizer.
The clock rate is programmable to be either 19.44 or 77.76
MHz. The frequency tolerance for this clock is ± 20 ppm.
The maximum allowed jitter on this clock should be con-
fined to the same limits as indicated below for the
REFTXCLK2P/REFTXCLK2N leads.
transmit clock synthesizer.
The clock rate is programmable to be 19.44, 77.76 or
155.52 MHz. A 622.08 MHz clock can be provided when
the Tx PLL is bypassed. The frequency tolerance for this
clock is ± 20 ppm. The maximum jitter on this clock should
be confined to a bandwidth of 5 kHz - 5 MHz and to the val-
ues shown below depending on the selected frequency as
indicated:
the receive clock and data recovery units. This clock is
required for line/loop-time applications, when REFTXCLK1
and REFTXCLK2P/N are not present.
The clock rate is programmable to be either 19.44 or 77.76
MHz. The frequency tolerance for this clock is ± 100 ppm
Serial APS Port Transmit Data: 622.08 Mbit/s bit-serial
data to mate PHAST-12N.
Applied Reference
Clock Frequency
155.52
622.08
(MHz)
19.44
77.76
-
Name/Function
Name/Function
ps RMS
Maximum Reference Clock Jitter
40
40
40
40
OC-3
ps pp
280
280
280
280
ps RMS
8
8
8
8
OC-12
2 6 o f 2 0 2
ps pp
56
56
56
56