TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 137

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TXC-06312BIOG

Manufacturer Part Number
TXC-06312BIOG
Description
Manufacturer
Transwitch Corporation
Datasheet

Specifications of TXC-06312BIOG

Lead Free Status / Rohs Status
Supplier Unconfirmed
1 3 7 o f 2 02
12.6 TRAIL TRACE IDENTIFIER PROCESS
12.6.1 TTI Formats
All performance counters are one second shadow counters: at the one second boundary the
contents of each performance counter is latched into its one second shadow register, after
which the performance counter is cleared. These one second shadow registers will hold their
value during the entire period between two subsequent one second boundaries.
The one second shadow registers are available for software read-only access.
All errored BIP and block counters are dimensioned to cover the maximum count value during
a one second interval meaning they can never reach saturation.
The one second boundary is generated by the internal one second clock which is either
derived from the PHAST-12N System Clock or from the external REFONESECCLK input lead.
The performance counters can be reset by writing 0x91 into the ResetCounters register.
The following TTI formats or modes are supported:
Note:
detection) and generation.
The following TTI message types are supported:
• 16-byte trace message: 16-byte repeating pattern consisting of a 15-byte APId preceded
• 64-byte trace message: a 64-byte repeating pattern consisting of a 63-byte APId pre-
• 64-byte trace message with CR/LF: a 64-byte repeating pattern consisting of a 62-byte
• repeating non-specific byte: a repeating single byte with fixed (constant), but unspecified
• repeating specific byte: a repeating single byte with fixed (constant) value. The remote
by a one byte header. The most significant bits of the TTI bytes form a 16-bit TFAS with a
1 in the most significant bit of the first TTI byte (header byte) and a 0 in the most signifi-
cant bit of the APId bytes.
ceded by a one byte header. The most significant bits of the TTI bytes form a 64-bit TFAS
with a 1 in the most significant bit of the first TTI byte (header byte) and a 0 in the most
significant bit of the APId bytes.
APId followed by a two byte trailer. The trailer consists of the <CR> and <LF> ASCII char-
acters.
value.
end user knows in advance which value is expected.
*The user has to specify TFAS, CRC or CR/LF both for monitoring (mismatch
*The repeating specific byte is handled as a 16-byte trace message without TFAS.
J0
J1
- Telecom Bus -
Repeating non-specific byte
Repeating specific byte
16-byte trace message
Repeating non-specific byte
16-byte trace message
64-byte trace message with TFAS
64-byte trace message with CR/LF
PRELIMINARY TXC-06312B-MB, Ed. 2
PHAST-12N Device
DATA SHEET
TXC-06312B
June 2005

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