TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 73

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

7 3 o f 2 0 2
Symbol
a. Only applies if a write access is preceded by a read access. R/W may stay low between 2
b. CS may stay low between 2 successive accesses to the same peripheral.
c. Only applies if a write access is followed by a read access. R/W may stay low between 2 suc-
d. No timing constraint between the rising edges of CS and DS are defined, since no such rela-
e. Between accesses to different peripherals.
t
t
t
H3
t
t
t
SU2
SU3
t
D10
SU1
SU4
t
t
t
t
t
t
t
t
t
H2
successive write accesses.
cessive write accesses.
tionship is defined in the MC68360 data sheet. CS is only latched at the beginning of an
access.
t
t
H1
H4
D1
D2
D3
D4
D5
D6
D7
t
H
L
b, d
c
a
b
e
20 ns
0.4t
0.4t
-0.9t
0 ns
0 ns
-0.9t
0 ns
0 ns
-
0 ns
0 ns
0 ns
0 ns
4 ns
-
t
TBD
t
Min
-
-
-
-
-
-
-
-
-
-
-
20 ns
8 ns
7 ns
-
20 ns
-
TBD
-
Max
- Timing Characteristics -
CLK clock period
CLK clock low phase pulse width
CLK clock high phase pulse width
Setup time of A to falling edge DS
Setup time of R/W to falling edge DS
Setup time of CS to falling edge DS
Setup time of D to falling edge DS
Hold time of A to active edge DSACK
Hold time of R/W to rising edge DS
Hold time of CS to rising edge DS
Hold time of D to active edge DSACK
Delay from falling edge DS to DSACK driving
Delay from falling edge CLK to active edge DSACK
Delay from rising edge DS to inactive edge DSACK
Delay from DSACK going inactive to DSACK going in tristate
Delay from rising edge DS to DSACK going in tristate
DS inactive pulse width
Response latency
CS inactive pulse width
Description
PRELIMINARY TXC-06312B-MB, Ed. 2
PHAST-12N Device
DATA SHEET
TXC-06312B
June 2005