STV3550B STMicroelectronics, STV3550B Datasheet - Page 103

• Manufacturer Part Number: STV3550B
• Manufacturer: STMicroelectronics

Specifications of STV3550B

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

STV3550
Note:
7.7.6
The reload value must be greater than zero and it will also have a minimum value (i.e.
Where SSCBRG represents the content of the reload register, as an unsigned 16-bit integer
and f
At a CPU clock frequency of 40 MHz, the following baud rates are generated as shown in
Table
Table 26.
maximum frequency) which is related to the CPU clock frequency. In normal mode this
should be a minimum of 0x0008. In I²C mode it is the sum of the settings of the data_hold
constant and the data_setup constant. i.e. 21 + 18 = 0x0027 at 60 MHz or 7 + 6 = 0x000D at
20 MHz.
The value in SSCBRG is used to load a counter at the start of each clock cycle. The counter
counts down until it reaches 1 and then flips the clock to the opposite logic value.
Consequently, the clock produced is twice the SSCBRG number of CPU clock cycles.
Reading the SSCBRG register will return the current count value. This can be used to
determine how far into each half cycle the counter is.
Shift register
The shift register is loaded at the start of a data frame with the data in the transmit buffer. It
then shifts data out of the serial_data_out port and data in from the serial_data_in port.
The shift register can shift out LSB first or MSB first. This is programmed by the heading
control bit, SSCHB in the control register. A logic 1 indicates that the MSB will be shifted out
first and a logic 0 that the LSB will shift first.
The width of a data frame is also programmable from 2 bits to 16 bits. This is set by the
SSCBM bit field of the control register. A value of “0000” is not allowed, subsequent values
set the bit width to the value plus one e.g. “0001” sets the frame width to 2 bits and “1111”
sets it to 16 bits.
When shifting LSB first, data comes into the shift register at the MSB of the programmed
frame width and is taken out of the LSB of the register. When shifting in MSB first, data is
Reserved. Use a reload value > 0
5 MBaud
3.3 MBaud
2.5 MBaud
2.0 MBaud
1.0 MBaud
100 KBaud
10 KBaud
1.0 KBaud
CPU
26.
represents the CPU clock frequency.
Baud rates and bit times for various SSCBRG reload values
Baud rate
Baudrate
=
--------------------------------- -
2xSSCBRG
f
CPU
-
200 ns
300 ns
400 ns
500 ns
1 us
10 us
100 us
1 ms
SSCBRG
Bit time
=
---------------------------------
2xBaudrate
f
CPU
00C8H
07D0H
0000H
0004H
0006H
0008H
000AH
0014H
4E20H
TV chassis control
Reload value
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