STV3550B STMicroelectronics, STV3550B Datasheet - Page 84
![no-image](/images/manufacturer_photos/0/6/637/stmicroelectronics_sml.jpg)
STV3550B
Manufacturer Part Number
STV3550B
Description
Manufacturer
STMicroelectronics
Datasheet
1.STV3550B.pdf
(145 pages)
Specifications of STV3550B
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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CPU and system management functional description
6.3.12
Figure 55. Internal and external memory map
6.4
84/145
Address Space
BFFFFFFF
STV3550
7FFFFFFF
3FFFFFFF
FFFFFFFF
C0000000
40000000
00000000
80000000
STV3550 external and internal memory mapping
Reset strategy
The internal and external memory maps in the STV3550 is described in
The chip includes three different types of reset:
1.
2.
3.
An external hard reset controlled by the NRESET pin and usually used for the power on
reset (POR).
An internal reset generated by the watchdog.
A soft reset controlled by the ST20 C2C200 CPU core.
7FFFFFFF
67FFFFFF
41FFFFFF
1FFFFFFF
7FFE0000
80001FFF
30005FFF
80000000
50000000
40000000
20000000
00000000
Memory Resource Type
STV3550 Memory Interface Control Registers
Other STV3550 Peripheral Registers
ST20 Peripheral Registers (INTC,
ST20 Internal SRAM (8 KBytes)
SDRAM (up to 32 MBytes)
Flash (up to 2 MBytes)
DCU, Caches)
(Display...)
Figure
Internal
Memory
Resource
Internal
Memory
Resource
External
Memory
Resource
External
Memory
Resource
Internal
Memory
Resource
55.
STV3550
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