STV3550B STMicroelectronics, STV3550B Datasheet - Page 81
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STV3550B
Manufacturer Part Number
STV3550B
Description
Manufacturer
STMicroelectronics
Datasheet
1.STV3550B.pdf
(145 pages)
Specifications of STV3550B
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
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Manufacturer
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STV3550
Figure 52. High-end configuration using 1 SDRAM device
High-end configuration with two SDRAM devices
This configuration requires two SDRAM devices with 16 data lines each. A typical size of the
SDRAMs may be 64 Mbits (8 MBytes).
One SDRAM device is connected to the upper half of the data bus, while the other device is
connected to the lower half. The Flash memory shares the lower half of the data bus with
one of the SDRAM devices.
From STV3550 point of view, since the data word size is 32 bits, address outputs
ADDR[12:1] are connected to the SDRAM address buses, and address outputs
ADDR[16:15] are used as Bank Activate signals.
Note that outputs NOT_BE[1:0] are connected to DQM[1:0] of the SDRAM connected to the
upper half of the data bus, while address outputs ADDR[19:18] are driving DQM[1:0] of the
other SDRAM. This means that internal Byte Enable 0 and 1 are provided through
ADDR[19:18] and Byte Enable 2 and 3 are provided through NOT_BE[1:0]. The Flash is a
read-only device.
STV3550
NOT_CS_SDRAM
NOT_CS_FLASH
CKOUT_SDRAM
SDRAM_D[15:0]
FLASH_D[15:0]
RD_NOT_WR
CKIN_SDRAM
NOT_BE[1:0]
ADDR[19:0]
NOT_RAS
NOT_CAS
[19:0]
[15:0]
(MSBs)
CPU and system management functional description
[15:0]
(LSBs)
[19:18]
[31:0]
[16:15]
[12:1]
[19:0]
[15:0]
CKEN
CS
OE
WE
ADDR[19:0]
DATA[15:0]
CS
RAS
CAS
WE
DQM[3:2]
A[11:0]
BA[1:0]
DQ[31:0]
CLK
DQM[1:0]
FLASH
16Mb
SDRAM
128Mb
81/145
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