STV3550B STMicroelectronics, STV3550B Datasheet - Page 67

• Manufacturer Part Number: STV3550B
• Manufacturer: STMicroelectronics

Specifications of STV3550B

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

STV3550
5.5.3
5.5.4
Data enable output
This signal is fully generated according to the control register value. The user must assume
the video window is correct according to the display data (video + OSD + background).
Figure 44. Data enable output
The data enable signal is in the CLK_DAC domain. This signal generates a jitter free signal
only if the Hsync and Vsync signal are output in the same clock domain (‘clk_dac’). The
reference signals to generate this signal are HS_PIX, VS_RST_100_PIX and
LINEUPCNT_PIX.
DE polarity can be selected with a dedicated register.
Data clock output
We could output the block clock with a choice of polarity and four different delays according
to the configuration register.
start line
line 0
display line
10 bits
10 bits
Output stage
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