STV3550B STMicroelectronics, STV3550B Datasheet - Page 76

• Manufacturer Part Number: STV3550B
• Manufacturer: STMicroelectronics

Specifications of STV3550B

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

CPU and system management functional description
6.3.9
Figure 47. State table in the STV3550 memory interface
76/145
Precharge All/
Initialization
Power-On /
Refresh
STV3550 memory interface capabilities regarding SDRAM device
Supported SDRAM commands
The STV3550 memory interface supports the following SDRAM commands:
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●
●
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The STV3550 memory interface always accesses SDRAM in page mode regardless of the
burst length programmed in the Mode Register Set command. It is recommended to use a
burst length of 1 to prevent any problems when signal interfaces are shared by the SDRAM
and Flash memories. (For more information, refer to
The STV3550 can be fully parameterized depending on the SDRAM device specification.
Latencies, refresh interval, row/column addresses split, number of SDRAM sub-banks, etc.,
can be configured through the control registers.
The STV3550 Memory Interface is compliant with JEDEC and PC100 specifications which
recommend applying a NOP signal for a minimum of 200 µs after the power-on sequence.
Once this period has elapsed, the application software will ask the STV3550 Memory
Interface to Precharge All the banks, to perform eight Refresh commands and to send the
Mode Register Set command. Then the SDRAM device is ready to be used by STV3550 for
standard data exchange.
Mode register set
Row activate
Precharge all
Read and write
CBR refresh
No operation (NOP)
The arcs and states in the state table are a subset of the
Register
Mode
Set
Write
possible ones in the SDRAM devices.
Precharge
Activate
Row
Idle
All
Request for
access
Refresh
counter
equals zero
Section 6.3.5: Memory
Read
Refresh
CBR
configurations.)
STV3550