STV3550B STMicroelectronics, STV3550B Datasheet - Page 112

• Manufacturer Part Number: STV3550B
• Manufacturer: STMicroelectronics

Specifications of STV3550B

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

TV chassis control
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Clock synchronization
Until the status bit is reset, the SSC2 will hold the clock line LOW at the end of the current
data frame. This forces the winning master device to wait until the software has processed
the interrupt.
The interrupt and status bit will be reset by a read of the status register, SSCSTAT.
To indicate that the I²C-bus is busy (i.e. between a START and a STOP condition), the I²C
bus busy bit, SSCBUSY, is set. This does not generate an interrupt.
Clock period in I²C mode
The I²C standard requires that at 400 KBits/s the clock low period is longer than the clock
high period. This is performed by adding a constant (based in the system clock frequency)
to the clock low period count and subtracting the count from the clock high period count.
This mechanism is enabled for all frequencies when the SSCI2CM bit is set.
The I²C standard defines how the serial clock signal can be stretched by slow slave devices
and how a single synchronized clock is generated in a multi-master environment. The clock
synchronization among all the devices is performed as follows.
All master devices start generating their low clock pulse when the external clock line goes
low (this may or may not correspond with their own generated high to low transition).
They count out their low clock period and when finished they attempt to pull the clock line to
high. However, if another master device is attempting to use a slower clock frequency, then it
will be holding the clock line low, or if a slave device wants to, it can extend the clock period
by deliberately holding the clock low.
Due to the open-drain output drive, the slower clock will win and the external clock line will
remain low until this device has finished counting its slow clock pulse, or until the slave
device is ready to proceed.
In the meantime, the faster master device will have detected a contradiction and will go into
a wait state until the clock signal goes high again.
Once the external clock signal goes high, all the master devices will begin counting off their
high clock pulse. In this case the first master to finish counting will attempt to pull the
external clock line low and will win (because of the open drain line). The other master
devices will detect this and will abort their high pulse count and switch to counting out their
low clock pulse.
Consequently, the faster master device will determine the length of the high clock pulse, and
the slowest master or slave device will determine the length of the low clock pulse.
This results in a single synchronized clock signal which all master and slave devices then
use to clock their shift registers.
The synchronization and stretching mechanism is shown in
Figure
73.
STV3550