STV3550B STMicroelectronics, STV3550B Datasheet - Page 88

• Manufacturer Part Number: STV3550B
• Manufacturer: STMicroelectronics

Specifications of STV3550B

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

CPU and system management functional description
Table 24.
6.8
Note:
88/145
Interrupt source name
OSD
Video Display Pipeline
SDIN
VTG
Peripherals and I/Os
2DBM
Line-locked PLL
TOTAL
1
2
3
Interrupt sources
Clock generator
The chip includes different asynchronous clock domains. In general, each block connected
to the Interconnect has two clock domains separated by a FIFO: the input or output clock
domain and the Interconnect clock domain. The different clocks are generated by an on-chip
clock synthesizer based on a 27 MHz reference clock. This can be the incoming D1 clock or
a fixed external clock. All clocks are then referenced to the master clock.
The pixel clock can be a free-running 22 to 72 MHz clock issued from a synthesizer. The
pixel clock is obtained by a division of the DAC clock signal.
A second option is to have the pixel clock locked on the front-end clock (D1), through the
synthesizer, used as PLL. The time constant is adjustable by programming.
All other clocks are generated by a high frequency P/Q PLL, locked to the crystal oscillator.
4
5
19
5
20
2
1
56
Number of
interrupts
4
5
10
4
2
25
synchronous
Number of
interrupts
9
5
16
1
31
asynchronous
Number of
interrupts
7
7
Number of wake-
up interrupts
2
2
interrupts
Off-chip
STV3550