STV3550B STMicroelectronics, STV3550B Datasheet - Page 70

• Manufacturer Part Number: STV3550B
• Manufacturer: STMicroelectronics

Specifications of STV3550B

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

CPU and system management functional description
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6.1
6.1.1
6.2
6.3
6.3.1
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ST20 C2C200 CPU core
STBus interconnect overview
STV3550 memory interface
CPU and system management functional description
This is the 32-bit ST20 C2C200 CPU core from the ST20 CPU family with a programmable
operating frequency between 4 MHz and 100 MHz, depending on the operating mode (full
speed or low power). The cell includes a 4-kB instruction cache memory, a 4-kB data cache
memory, a 8-kB SRAM, a diagnostic controller unit (DCU) and an interrupt controller (ITC).
Main features
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The STV3550 Interconnect is based on the STBus architecture. Its main function is to allow
data to flow between different blocks called “initiators” and “targets”. Each initiator can make
a transaction with any target. The priority of the transaction depends on the arbitration made
by each interconnect module or arbiter.
In the STV3550, the memory interface is in four parts:
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Memory devices
The STV3550 requires a ROM device that contains the application software and a RAM
device for video and software data. If the ROM bandwidth is not sufficient, the application
32-bit VL-RISC processor
60 MIPS (Dhrystone 2.1) at 100 MHz clock
16 cache registers of 32-bits providing fast access to local variables
Fast-context switch time (less than 1 µs)
Up to 16 interrupt inputs
Includes 4-kB instruction cache memory, 4-kB data cache memory, and 8-kB SRAM for
DMA transactions or cache increase
Includes a diagnostic controller unit for real time debugging via a JTAG port and ST20
emulator
External memory interface (EMI) manages all memory accesses from a protocol point
of view
Pad glue logic (PGL) is used for multiplexing and sharing functions on the memory
pads in order to optimize the number of pins. The PGL mainly implements
combinational logic as well as some control logic
Pad logic (PL) solves timing issues encountered when connecting high speed devices
on a printed circuit board (PCB). The PL mainly implements the bi-directional pad and
its associated control logic to accommodate the setup and hold time of memory
devices
Delay locked line (DLL)
STV3550