STV3550B STMicroelectronics, STV3550B Datasheet - Page 115

• Manufacturer Part Number: STV3550B
• Manufacturer: STMicroelectronics

Specifications of STV3550B

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

STV3550
7.7.22
START/STOP condition generation
2.
3.
Clock stretching is always cleared by a write to the transmit buffer. However, the clock
stretch is only cleared after the required data setup time has expired, otherwise the new
transmit buffer data may affect the value on the data line close to the clock edge.
If a clock stretching event occurs but no relevant interrupt is enabled then the clock will be
stretched indefinitely until the next transmit buffer write. Hence it is important that the correct
interrupts are always enabled. There is a clock stretch status bit, SSCCLST, which indicates
when clock stretching is in operation. This will be cleared after the data setup time after the
transmit buffer is written to.
As a master device the SSC2 must generate a START condition before transmission of the
first byte can start. It may also generate repeated START conditions. It must complete its
access to the bus with a STOP condition.
Between STOP and START conditions the bus is free and the clock and data lines must be
held high. The I²C control block determines this holds the lines high between transactions.
The START/STOP generator is controlled by the START condition generate bit, SSCSTRTG
and the STOP condition generate bit, SSCSTOPG in the I²C control register.
The generator will pull the serial_data_out line LOW during the high period of the clock to
produce a START condition. In the case of a STOP condition it will pull the data line HIGH.
However, a START condition will only be generated if the bus is currently free (i.e. the
SSCBUSY bit in the status register is LOW). This is to prevent the SSC2 from generating a
START condition when another master has just generated one.
If a START condition cannot be generated because the bus is busy, then the generator will
force the arbitration checker to generate an arbitration lost interrupt and prevent data from
being transmitted for the next byte. The software interrupt handler is therefore informed of
the aborted transmission when servicing the interrupt.
To properly generate the timing waveforms of the START and STOP conditions, the SSC2
contains a timing counter. This ensures the minimum setup and hold times are met with
some additional margin.
occur after the second byte plus acknowledge). This gives the software interrupt routine
time to initialize for transmission or reception of data.
When the SSC2 is in slave mode and is transmitting or receiving. The clock stretch
occurs immediately after each data byte plus acknowledge. When transmitting, this
allows the software interrupt routine to check that the master has acknowledged before
writing the next data byte into the transmit buffer. If no acknowledge is received, then
the software must stop transmitting bytes. When receiving it allows the software to read
the next data byte before the master starts to send the next one.
When the SSC2 loses arbitration. The clock stretch occurs immediately after the
current data byte and acknowledge have been performed. This gives the software time
to abort its current transmission and prepare to retry after the next STOP condition.
TV chassis control
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