STV3550B STMicroelectronics, STV3550B Datasheet - Page 123

• Manufacturer Part Number: STV3550B
• Manufacturer: STMicroelectronics

Specifications of STV3550B

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

STV3550
If the mode is one where a parity bit is expected, then the next bit (bit 8 of 0-9) records
whether there was a parity error when that entry was received. It does not contain the parity
bit that was received. For 7-bit+parity data frames the parity error bit is set in both the eighth
(bit 7 of 0-9) and the ninth (bit 8 of 0-9) bits. The ParityError bit of ASC_n_Status is set when
the input buffer (double-buffered operation), or at least one of the valid entries in the input
buffering (FIFO-controlled operation), has bit 8 set.
When receiving 8-bit data frames without parity (see section ), the ninth bit of each input
entry (bit 8 of 0-9) is undefined.
Input buffering modes
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Time-out mechanism
The ASC contains an 8-bit time-out counter. This reloads from ASC_n_Timeout whenever
one or more of the following is true:
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If none of these conditions hold the counter decrements towards 0 at every baud rate tick.
FIFO enabled reception: The FIFOs are enabled by setting the FifoEnable bit of the
ASC_n_Control register. The input FIFO is implemented as a 16-deep array of 10-bit
vectors (each 9 down to 0). If the input FIFO is empty i.e. no entries are present, the
RxBufFull bit of the ASC_n_Status register is set to ‘0’. If one or more FIFO entries are
present, the RxBufFull bit of the ASC_n_Status register is set to 1. If the input FIFO is
not empty, a read from ASC_n_RxBuffer will get the oldest entry in the input FIFO.
The RxHalfFull bit of the ASC_n_Status register is set when the input FIFO contains
more than 8 characters. Writing anything to ASC_n_RxReset empties the input FIFO.
As soon as the effective value of the last stop bit has been determined, the content of
the input shift register is transferred to the input FIFO (except during wake-up mode, in
which case this happens only if the wake-up bit, bit 8, is a ‘1’). The receive circuit then
waits for the next falling edge transition at the RxD pin.
The OverrunError bit of the ASC_n_Status register is set when the input FIFO is full
and a character is loaded from the input shift register into the input FIFO. It is cleared
when the ASC_n_RxBuffer register is read.
After changing the FifoEnable bit, it is important to reset the FIFO to empty by writing to
the ASC_n_RxReset register; otherwise the state of the FIFO pointers may be
garbage.
Double-buffered reception: Double-buffered operation is enabled and the FIFOs
disabled by writing 0 to the FifoEnable bit of the ASC_n_Control register. This mode
can be seen as equivalent to a FIFO-controlled operation with a FIFO of length 1 (the
first FIFO vector is in fact used as the buffer). When the last stop bit has been received
(at the end of the last programmed stop bit period) the content of the receive shift
register is transferred to the receive data buffer register (ASC_n_RxBuffer). The receive
buffer full flag (RxBufFull) is set, and the parity (ParityError) and framing error
(FrameError) flags are updated at the same time, after the last stop bit has been
received, i.e. at the end of the last stop bit programmed period. The flags are updated
even if no valid stop bits have been received. The receive circuit then waits for the next
falling edge transition at the RxD pin.
ASC_n_RxBuffer is read
the ASC is in the middle of receiving a character
ASC_n_Timeout is written to
TV chassis control
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