STV3550B STMicroelectronics, STV3550B Datasheet - Page 121

• Manufacturer Part Number: STV3550B
• Manufacturer: STMicroelectronics

Specifications of STV3550B

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

STV3550
7.8.3
Transmission
Transmission begins at the next baud rate clock tick, provided that the run bit is set and data
has been loaded into the ASC_n_TxBuffer. If the CTSEnable bit is set in the ASC_n_Control
register then transmission only occurs when CTS is high.
The transmitter empty flag (TxEmpty) indicates whether the output shift register is empty. It
will be set at the beginning of the last data frame bit that is transmitted, i.e. during the first
system clock cycle of the first stop bit shifted out of the transmit shift register.
The loop-back option (selected by the LoopBack bit of the ASC_n_Control register)
internally connects the output of the transmitter shift register to the input of the receiver shift
register. This may be used to test serial communication routines at an early stage without
having to provide an external network.
Transmission with FIFOs enabled
The FIFOs are enabled by setting the FifoEnable bit of the ASC_n_Control register. The
output FIFO is implemented as a 16-deep array of 9-bit vectors. Values to be transmitted are
written to the output FIFO by writing to ASC_n_TxBuffer.
The TxFull bit of the ASC_n_Status register is set when the transmit FIFO is considered full,
i.e. when it contains 16 characters. Further writes to ASC_n_TxBuffer will fail to overwrite
the most recent entry in the output FIFO. The TxHalfEmpty bit of the ASC_n_Status register
is set when the output FIFO contains 8 or fewer characters.
Values are shifted out of the bottom of the output FIFO into a 9-bit output shift register in
order to be transmitted. If the transmitter is idle (i.e. the output shift register is empty) and
something is written to the ASC_n_TxBuffer so that the output FIFO becomes non-empty,
the output shift register is immediately loaded from the output FIFO and transmission of the
data in the output shift register begins at the next baud rate tick.
When the transmitter is just about to transmit the stop bits, and if the output FIFO is non-
empty, the output shift register will be immediately loaded from the output FIFO, and the
transmission of this new data will begin as soon as the current stop bit period is over (i.e. the
next start bit will be transmitted immediately following the current stop bit period). If the
output FIFO is empty at this point, the output shift register will become empty. Thus back-to-
back transmission of data can take place. If the output FIFO is empty at this point, the output
shift register will become empty. Writing anything to ASC_n_TxReset empties the output
FIFO.
After changing the FifoEnable bit, it is important to reset the FIFO to empty (by writing to the
ASC_n_TxReset register), or garbage may be transmitted.
Double-buffered transmission
Double buffering is enabled and the FIFOs disabled by writing 0 to the FifoEnable bit of the
ASC_n_Control register. When the transmitter is idle, the transmit data written into the
transmit buffer ASC_n_TxBuffer is immediately moved to the transmit shift register, thus
freeing the transmit buffer for the next data to be sent. This is indicated by the transmit buffer
empty flag (TxHalfEmpty) being set. The transmit buffer can be loaded with the next data
while transmission of the previous data is still going on.
When the FIFOs are disabled, the TxFull bit is set when the buffer contains 1 character, and
a write to ASC_n_TxBuffer in this situation will overwrite the contents. The TxHalfEmpty bit
of the ASC_n_Status register is set when the output buffer is empty.
TV chassis control
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