EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 132
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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5–16
Stratix IV Device Handbook Volume 1
f
1
You can set the input clock sources and the clkena signals for the GCLK and RCLK
network multiplexers through the Quartus II software using the ALTCLKCTRL
megafunction. You can also enable or disable the dedicated external clock output pins
using the ALTCLKCTRL megafunction.
clock control block.
When using the ALTCLKCTRL megafunction to implement dynamic clock source
selection, the inputs from the clock pins feed the inclk[0..1] ports of the multiplexer,
while the PLL outputs feed the inclk[2..3] ports. You can choose from among these
inputs using the CLKSELECT[1..0] signal.
For more information, refer to the
User
Figure 5–13. Stratix IV External PLL Output Clock Control Block
Notes to
(1) When the device is operation in user mode, you can only set the clock select signals through a configuration file (.sof
(2) The clock control block feeds to a multiplexer within the PLL_<#>_CLKOUT pin’s IOE. The PLL_<#>_CLKOUT
or .pof) and cannot be dynamically controlled.
pin is a dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control
block.
Guide.
Figure
5–13:
IOE
Internal
Logic
(2)
PLL_<#>_CLKOUT pin
7 or 10
Clock Control Block (ALTCLKCTRL) Megafunction
PLL Counter
Outputs
Enable/
Disable
Figure 5–13
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Internal
Static Clock
Select (1)
Logic
Static Clock Select
shows the external PLL output
(1)
Clock Networks in Stratix IV Devices
February 2011 Altera Corporation
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