EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 90
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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4–10
Stratix IV Device Handbook Volume 1
Input Registers
All of the DSP block registers are triggered by the positive edge of the clock signal and
are cleared after power up. Each multiplier operand can feed an input register or go
directly to the multiplier, bypassing the input registers. The following DSP block
signals control the input registers within the DSP block:
■
■
■
Every DSP block has nine 18-bit data input register banks per half DSP block. Every
half DSP block has the option to use the eight data register banks as inputs to the four
multipliers. The special ninth register bank is a delay register required by modes that
use both the cascade and chainout features of the DSP block. Use the ninth register
bank to balance the latency requirements when using the chained cascade feature.
clock[3..0]
ena[3..0]
aclr[3..0]
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Resource Descriptions
February 2011 Altera Corporation
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