EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 286
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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8–8
LVDS SERDES
Figure 8–4. LVDS SERDES
Notes to
(1) This diagram shows a shared PLL between the transmitter and receiver. If the transmitter and receiver are not sharing the same PLL, the two left
(2) In SDR and DDR modes, the data width is 1 and 2 bits, respectively.
(3) The tx_in and rx_out ports have a maximum data width of 10 bits.
Stratix IV Device Handbook Volume 1
tx_coreclock
rx_divfwdclk
rx_outclock
and right PLLs are required.
FPGA
Fabric
rx_out
tx_in
Figure
8–4:
10
10
Figure 8–4
circuitry in the left and right banks. This diagram shows the interface signals of the
transmitter and receiver data path. For more information, refer to
Transmitter” on page 8–11
3
(LOAD_EN, diffioclk)
IOE Supports SDR, DDR, or
2
(Note
(LVDS_LOAD_EN, diffioclk,
DIN DOUT
Non-Registered Datapath
Deserializer
DOUT
Serializer
1), (2),
tx_coreclock)
DIN
shows a transmitter and receiver block diagram for the LVDS SERDES
IOE
2
Left/Right PLL
2
(3)
3
DOUT
Clock MUX
(LVDS_LOAD_EN,
Bit Slip
LVDS_diffioclk,
IOE
rx_outclock
diffioclk
DIN
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
and
rx_inclock/tx_inclock
“Differential Receiver” on page
LVDS Transmitter
LVDS Receiver
DOUT
Synchronizer
IOE Supports SDR, DDR, or
Non-Registered Datapath
DIN
8 Serial LVDS
Clock Phases
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
Retimed
DPA Clock
Data
DPA Circuitry
February 2011 Altera Corporation
DIN
8–17.
“Differential
+
-
LVDS Clock Domain
DPA Clock Domain
+
-
LVDS SERDES
rx_in
tx_out
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