EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 282
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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8–4
Figure 8–3. High-Speed Differential I/Os with DPA Locations in Stratix IV GT and GX Devices
LVDS Channels
Stratix IV Device Handbook Volume 1
1
Figure 8–3
The Stratix IV device family supports LVDS on both row and column I/O banks. Row
I/Os support true LVDS input with 100-Ω differential input termination (OCT R
and true LVDS output buffers. Column I/Os supports true LVDS input buffers
without OCT R
emulated LVDS output buffers that use two single-ended output buffers with an
external resistor network to support LVDS, mini-LVDS, and RSDS standards.
Stratix IV devices offer single-ended I/O refclk support for the LVDS.
Dedicated SERDES and DPA circuitries are implemented on the row I/O banks to
further enhance LVDS interface performance in the device. For column I/O banks,
SERDES is implemented in the core logic because there is no dedicated SERDES
circuitry on column I/O banks.
Emulated differential output buffers support tri-state capability starting with the
Quartus II software version 9.1.
shows a high-level chip overview of the Stratix IV GT and GX devices.
General Purpose
General Purpose
I/O and Memory
I/O and Memory
PLL
PLL
PLL
PLL
D
Interface
Interface
. Alternately, you can configure the row and column LVDS pins as
(Logic Elements, DSP,
Embedded Memory,
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Clock Networks)
FPGA Fabric
PLL
PLL
PLL
PLL
General Purpose
General Purpose
I/O and Memory
I/O and Memory
Interface
Interface
PLL
PLL
PLL
PLL
February 2011 Altera Corporation
LVDS Channels
D
),
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