EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 219
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H40I3
Manufacturer:
ALTERA
Quantity:
325
Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
SHARP
Quantity:
1 200
Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA
Quantity:
490
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
- Current page: 219 of 432
- Download datasheet (11Mb)
Chapter 6: I/O Features in Stratix IV Devices
Design Considerations
February 2011 Altera Corporation
Non-Voltage-Referenced Standards
Each I/O bank of a Stratix IV device has its own VCCIO pins and supports only one
V
number of input signals with different I/O standard assignments if it meets the V
and V
For output signals, a single I/O bank supports non-voltage-referenced output signals
that are driving at the same voltage as V
V
For example, an I/O bank with a 2.5-V V
inputs and outputs as well as 3.0-V LVCMOS inputs (but not output or bidirectional
pins).
Voltage-Referenced Standards
To accommodate voltage-referenced I/O standards, each Stratix IV device’s I/O bank
supports multiple VREF pins feeding a common V
VREF pins increases as device density increases. If these pins are not used as VREF pins,
they cannot be used as generic I/O pins and must be tied to V
can only have a single V
time.
An I/O bank featuring single-ended or differential standards can support
voltage-referenced standards if all voltage-referenced standards use the same V
setting.
For performance reasons, voltage-referenced input standards use their own V
level as the power source. This feature allows you to place voltage-referenced input
signals in an I/O bank with a V
HSTL-15 input pins in an I/O bank with 2.5-V V
input with parallel OCT enabled requires the V
voltage of the input standard.
Voltage-referenced bidirectional and output signals must be the same as the I/O
bank’s V
bank with a 2.5-V V
Mixing Voltage-Referenced and Non-Voltage-Referenced Standards
An I/O bank can support both voltage-referenced and non-voltage-referenced pins by
applying each of the rule sets individually. For example, an I/O bank can support
SSTL-18 inputs and 1.8-V inputs and outputs with a 1.8-V V
Similarly, an I/O bank can support 1.5-V standards, 1.8-V inputs (but not outputs),
and HSTL and HSTL-15 I/O standards with a 1.5-V V
CCIO
CCIO
, either 1.2, 1.5, 1.8, 2.5, or 3.0 V. An I/O bank can simultaneously support any
CCPD
value, it can only drive out that one value for non-voltage-referenced signals.
CCIO
requirement, as shown in
voltage. For example, you can only place SSTL-2 output pins in an I/O
CCIO
.
CCIO
voltage level and a single V
CCIO
of 2.5 V or below. For example, you can place
Table 6–2 on page
CCIO
CCIO
. Because an I/O bank can only have one
setting can support 2.5-V standard
CCIO
CCIO
REF
. However, the voltage-referenced
of the I/O bank to match the
bus. The number of available
CCIO
6–3.
REF
and 0.75-V V
Stratix IV Device Handbook Volume 1
voltage level at a given
CCIO
CCIO
and a 0.9-V V
or GND. Each bank
REF
.
CCPD
REF
REF
.
CCIO
6–47
Related parts for EP4SE530H40I3
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: