EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 35
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EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Quantity
Price
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Part Number:
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Manufacturer:
ALTERA
Quantity:
325
Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
SHARP
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1 200
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Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA
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490
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
- Current page: 35 of 432
- Download datasheet (11Mb)
Chapter 1: Overview for the Stratix IV Device Family
Document Revision History
Table 1–10. Document Revision History (Part 2 of 2)
February 2011 Altera Corporation
June 2009
April 2009
March 2009
March 2009
November 2008
July 2008
May 2008
Date
Version
2.0
2.4
2.3
2.2
2.1
1.1
1.0
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Revised “Introduction”.
Initial release.
Updated Table 1–1.
Minor text edits.
Added Table 1–5, Table 1–6, and Figure 1–3.
Updated Figure 1–5.
Updated Table 1–1, Table 1–2, Table 1–3, and Table 1–4.
Updated “Introduction”, “Feature Summary”, “Stratix IV GX Devices”, “Stratix IV GT
Devices”, “Architecture Features”, and “FPGA Fabric and I/O Features”
Updated “Feature Summary”, “Stratix IV GX Devices”, “Stratix IV E Device”, “Stratix IV
GT Devices”, “Signal Integrity”
Removed Tables 1-5 and 1-6
Updated Figure 1–4
Updated “Introduction”, “Feature Summary”, “Stratix IV Device Diagnostic Features”,
“Signal Integrity”, “Clock Networks”,“High-Speed Differential I/O with DPA and Soft-
CDR”, “System Integration”, and “Ordering Information” sections.
Added “Stratix IV GT 100G Devices” and “Stratix IV GT 100G Transceiver Bandwidth”
sections.
Updated Table 1–1, Table 1–2, Table 1–3, and Table 1–4.
Added Table 1–5 and Table 1–6.
Updated Figure 1–3 and Figure 1–4.
Added Figure 1–5.
Removed “Referenced Documents” section.
Updated “Feature Summary” on page 1–1.
Updated “Stratix IV Device Diagnostic Features” on page 1–7.
Updated “FPGA Fabric and I/O Features” on page 1–8.
Updated Table 1–1.
Updated Table 1–2.
Updated “Table 1–5 shows the total number of transceivers available in the Stratix IV GT
Device.” on page 1–15.
Changes
Stratix IV Device Handbook Volume 1
1–21
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