EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 154
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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5–38
Stratix IV Device Handbook Volume 1
Spread-Spectrum Tracking
Clock Switchover
Stratix IV devices can accept a spread-spectrum input with typical modulation
frequencies. However, the device cannot automatically detect that the input is a
spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the
input of the PLL. Stratix IV PLLs can track a spread-spectrum input clock as long as it
is within input-jitter tolerance specifications. Stratix IV devices cannot internally
generate spread-spectrum clocks.
The clock switchover feature allows the PLL to switch between two reference input
clocks. Use this feature for clock redundancy or for a dual-clock domain application
such as in a system that turns on the redundant clock if the previous clock stops
running. The design can perform clock switchover automatically when the clock is no
longer toggling or based on a user control signal, clkswitch.
The following clock switchover modes are supported in Stratix IV PLLs:
■
■
■
Automatic switchover—The clock sense circuit monitors the current reference
clock and if it stops toggling, automatically switches to the other inclk0 or inclk1
clock.
Manual clock switchover—Clock switchover is controlled using the clkswitch
signal. When the clkswitch signal goes from logic low to logic high, and stays
high for at least three clock cycles, the reference clock to the PLL is switched from
inclk0 to inclk1, or vice-versa.
Automatic switchover with manual override—This mode combines automatic
switchover and manual clock switchover. When the clkswitch signal goes high, it
overrides the automatic clock switchover function. As long as the clkswitch signal
is high, further switchover action is blocked.
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
February 2011 Altera Corporation
PLLs in Stratix IV Devices
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