EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 155
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Figure 5–34. Automatic Clock Switchover Circuit Block Diagram
February 2011 Altera Corporation
1
inclk0
inclk1
Stratix IV PLLs support a fully configurable clock switchover capability.
shows a block diagram of the automatic switchover circuit built into the PLL. When
the current reference clock is not present, the clock sense block automatically switches
to the backup clock for PLL reference. The clock switchover circuit also sends out
three status signals—clkbad[0], clkbad[1], and activeclock—from the PLL to
implement a custom switchover circuit in the logic array. You can select a clock source
as the backup clock by connecting it to the inclk1 port of the PLL in your design.
Automatic Clock Switchover
Use the switchover circuitry to automatically switch between inclk0 and inclk1
when the current reference clock to the PLL stops toggling. For example, in
applications that require a redundant clock with the same frequency as the reference
clock, the switchover state machine generates a signal (clksw) that controls the
multiplexer select input, as shown in
reference clock for the PLL. When using automatic switchover mode, you can switch
back and forth between inclk0 and inclk1 any number of times when one of the two
clocks fails and the other clock is available.
When using automatic clock switchover mode, the following requirements must be
satisfied:
■
■
If the current clock input stops toggling while the other clock is also not toggling,
switchover is not initiated and the clkbad[0..1] signals are not valid. Also, if both
clock inputs are not the same frequency, but their period difference is within 100%, the
clock sense block detects when a clock stops toggling, but the PLL may lose lock after
the switchover is completed and needs time to re-lock.
Altera recommends resetting the PLL using the areset signal to maintain the phase
relationships between the PLL input and output clocks when using clock switchover.
Both clock inputs must be running
The period of the two clock inputs can differ by no more than 100% (2×)
muxout
clksw
n Counter
Sense
Clock
refclk
Figure
Switchover
Machine
State
5–34. In this case, inclk1 becomes the
Clock Switch
Control Logic
PFD
fbclk
Stratix IV Device Handbook Volume 1
clkbad[0]
clkbad[1]
activeclock
clkswitch
Figure 5–34
5–39
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