EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 239
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H40I3
Manufacturer:
ALTERA
Quantity:
325
Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
SHARP
Quantity:
1 200
Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA
Quantity:
490
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
- Current page: 239 of 432
- Download datasheet (11Mb)
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–14. Number of DQS/DQ Groups per Bank in EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the
1517-Pin FineLine BGA Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 devices do not support × 32/× 36 mode. To interface with a × 36 QDR II+/QDR II SRAM
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a × 4 DQS/DQ group with any of its pin members
February 2011 Altera Corporation
device, refer to
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Make sure that the DQS/DQ groups that you have chosen are not used for configuration as you may lose up to
four × 4 DQS/DQ groups, depending on your configuration scheme.
Figure
I/O Bank 1C
20 User I/Os
21 User I/Os
I/O Bank 2C
I/O Bank 2A
I/O Bank 1A
43 User I/Os
46 User I/Os
7–14:
x16/x18=0
x16/x18=0
x16/x18=1
x16/x18=0
x8/x9=0
x8/x9=0
x8/x9=2
x8/x9=1
x4=0
x4=1
DLL1
x4=6
DLL0
x4=5
“Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page
I/O Bank 8A
I/O Bank 3A
40 User I/Os
40 User I/Os
x16/x18=1
x16/x18=1
x8/x9=3
x8/x9=3
UP
x4=6
x4=6
and R
(Note
DN
pins for OCT calibration. If two pins of a ×4 group are used as R
I/O Bank 8B
I/O Bank 3B
24 User I/Os
24 User I/Os
EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices
1), (2), (3), (4),
x16/x18=1
x16/x18=1
x8/x9=2
x8/x9=2
x4=4
x4=4
in the 1517-Pin FineLine BGA
I/O Bank 3C
I/O Bank 8C
32 User I/Os
32 User I/Os
x16/x18=0
x16/x18=0
x8/x9=1
x8/x9=1
x4=3
x4=3
UP
(5)
and R
DN
32 User I/Os
I/O Bank 4C
32 User I/Os
I/O Bank 7C
x16/x18=0
x16/x18=0
x8/x9=1
x8/x9=1
pins, but you cannot use a ×4 group for memory interfaces if two pins
x4=3
x4=3
I/O Bank 4B
24 User I/Os
24 User I/Os
I/O Bank 7B
x16/x18=1
x16/x18=1
x8/x9=2
x8/x9=2
x4=4
x4=4
I/O Bank 7A
I/O Bank 4A
40 User I/Os
40 User I/Os
x16/x18=1
x16/x18=1
x8/x9=3
x8/x9=3
UP
x4=6
x4=6
7–26.
Stratix IV Device Handbook Volume 1
and R
DN
pins for OCT calibration, you
I/O Bank 5C
21 User I/Os
46 User I/Os
I/O Bank 5A
x16/x18=0
I/O Bank 6C
21 User I/Os
I/O Bank 6A
x16/x18=1
44 User I/Os
x16/x18=0
x8/x9=0
x16/x18=0
x8/x9=3
x8/x9=0
x8/x9=1
x4=0
x4=6
DLL2
x4=0
DLL3
x4=5
7–19
Related parts for EP4SE530H40I3
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: