EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 250
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EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
- Current page: 250 of 432
- Download datasheet (11Mb)
7–30
Figure 7–21. DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry
Notes to
(1) For possible reference input clock pins for each DLL, refer to
(2) You can configure each DQS/CQ and CQn pin with a phase shift based on one of two possible DLL output settings.
Stratix IV Device Handbook Volume 1
Figure
DQS/CQ
DQS/CQ
Pin
Pin
7–21:
CQn
CQn
Pin
Pin
Figure 7–21
and CQn pins in the device where memory interfaces are supported on all sides of the
Stratix IV device.
DQS phase-shift circuitry is connected to the DQS logic blocks that control each
DQS/CQ or CQn pin. The DQS logic blocks allow the DQS delay settings to be
updated concurrently at every DQS/CQ or CQn pin.
Δt
Δt
Δt
Δt
Phase-Shift
Phase-Shift
Reference
Reference
Circuitry
Circuitry
Clock
DQS
IOE
IOE
DQS
Clock
IOE
IOE
DLL
to
DLL
to
to
to
shows how the DQS phase-shift circuitry is connected to the DQS/CQ
to IOE
CQn
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
to IOE
CQn
Pin
Δt
“DLL” on page
DQS Logic
Blocks
to IOE
CQn
Pin
Δt
DQS/CQ
to IOE
7–31.
Pin
(Note
Δt
Chapter 7: External Memory Interfaces in Stratix IV Devices
DQS/CQ
to IOE
Pin
Δt
1),
to IOE
CQn
Pin
Δt
(2)
Phase-Shift
Phase-Shift
Reference
Reference
Circuitry
Circuitry
Stratix IV External Memory Interface Features
Clock
Clock
DLL
DLL
DQS
DQS
IOE
IOE
IOE
IOE
to
to
to
to
February 2011 Altera Corporation
DQS Logic
Blocks
Δt
Δt
Δt
Δt
CQn
DQS/CQ
CQn
DQS/CQ
Pin
Pin
Pin
Pin
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