EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 144
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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5–28
Stratix IV Device Handbook Volume 1
Source Synchronous Mode
If data and clock arrive at the same time on the input pins, the same phase
relationship is maintained at the clock and data ports of any IOE input register.
Figure 5–22
recommends source synchronous mode for source-synchronous data transfers. Data
and clock signals at the IOE experience similar buffer delays as long as you use the
same I/O standard.
Figure 5–22. Phase Relationship Between Clock and Data in Source-Synchronous Mode
Source-synchronous mode compensates for the delay of the clock network used plus
any difference in the delay between these two paths:
■
■
The Stratix IV PLL can compensate multiple pad-to-input-register paths, such as a
data bus when it is set to use source-synchronous compensation mode. You can use
the “PLL Compensation” assignment in the Quartus II software Assignment Editor to
select which input pins are used as the PLL compensation targets. You can include
your entire data bus, provided the input registers are clocked by the same output of a
source-synchronous-compensated PLL. In order for the clock delay to be properly
compensated, all of the input pins must be on the same side of the device. The PLL
compensates for the input pin with the longest pad-to-register delay among all input
pins in the compensated bus.
If you do not make the “PLL Compensation” assignment, the Quartus II software
automatically selects all of the pins driven by the compensated output of the PLL as
the compensation target.
Data pin to the IOE register input
Clock input pin to the PLL PFD input
shows an example waveform of the clock and data in this mode. Altera
Clock at register
Data at register
reference clock
at input pin
Data pin
PLL
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
February 2011 Altera Corporation
PLLs in Stratix IV Devices
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