EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 391
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Dedicated Remote System Upgrade Circuitry
Dedicated Remote System Upgrade Circuitry
Figure 10–25. Remote System Upgrade Circuit Data Path
Note to
(1) The RU_DOUT, RU_SHIFTnLD, RU_CAPTnUPDT, RU_CLK, RU_DIN, RU_nCONFIG, and RU_nRSTIMER signals are internally
April 2011 Altera Corporation
controlled by the ALTREMOTE_UPDATE megafunction.
Figure
RU_DOUT
10–25:
dout
Status Register (SR)
This section describes the implementation of the Stratix IV remote system upgrade
dedicated circuitry. The remote system upgrade circuitry is implemented in hard
logic. This dedicated circuitry interfaces to the user-defined factory and application
configurations implemented in the Stratix IV device logic array to provide the
complete remote configuration solution. The remote system upgrade circuitry
contains the remote system upgrade registers, a watchdog timer, and a state machine
that controls those components.
Figure 10–25
Bit [4..0]
[4..0]
RU_SHIFTnLD
capture
Shift Register
din
shows the data path for the remote system upgrade block.
RU_CAPTnUPDT
dout
Control Register
Update Register
Logic Array
Bit [37..0]
[37..0]
[37..0]
Logic Array
clkout
Logic Array
(Note 1)
capture
capture
update
RU_CLK
clkin
din
update
RU_DIN RU_nCONFIG
Internal Oscillator
Machine
State
RSU
Stratix IV Device Handbook Volume 1
time-out
RU_nRSTIMER
Watchdog
Timer
User
10–57
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