EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 202
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
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Manufacturer:
ALTERA
Quantity:
325
Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
SHARP
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Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA
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490
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
- Current page: 202 of 432
- Download datasheet (11Mb)
6–30
Figure 6–21. Dynamic Parallel OCT in Stratix IV Devices
Stratix IV Device Handbook Volume 1
Receiver
f
1
50 Ω
50
Transmitter
50 Ω
Stratix IV OCT
When using calibrated input parallel and calibrated output series termination on
bidirectional pins, they must use the same termination value because each I/O pin
can only reference one OCT calibration block. The only exception is when using 50 Ω
parallel OCT and 25 Ω series OCT using the left shift series termination control. For
example, you cannot use calibrated 50 Ω parallel OCT on the input buffer of a
bidirectional pin and calibrated 40 Ω series OCT on the output buffer because these
would require two separate calibration blocks with different RUP and RDN resistor
values.
For more information about tolerance specifications for OCT with calibration, refer to
the
Stratix IV OCT
DC and Switching Characteristics for Stratix IV Devices
VCCIO
VCCIO
GND
GND
100 Ω
100 Ω
100 Ω
100
100 Ω
100
Z
Z
O
O
= 50 Ω
= 50 Ω
On-Chip Termination Support and I/O Termination Schemes
100 Ω
100 Ω
100 Ω
100 Ω
100 Ω
100
100 Ω
100
VCCIO
VCCIO
GND
GND
Stratix IV OCT
Stratix IV OCT
Chapter 6: I/O Features in Stratix IV Devices
chapter.
Transmitter
February 2011 Altera Corporation
Receiver
50 Ω
50 Ω
50
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