EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 300
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EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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- Download datasheet (11Mb)
8–22
Figure 8–17. Deserializer Bypass in Stratix IV Devices
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, rx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
Stratix IV Device Handbook Volume 1
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
Receiver Data Path Modes
8–17:
2
Deserializer
You can statically set the deserialization factor to 3, 4, 6, 7, 8, or 10 by using the
Quartus II software. You can bypass the Stratix IV deserializer in the Quartus II
MegaWizard Plug-In Manager software to support DDR (×2) or SDR (×1) operations,
as shown
deserializer is bypassed. The IOE contains two data input registers that can operate in
DDR or SDR mode.
The Stratix IV device family supports three receiver datapath modes—non-DPA
mode, DPA mode, and soft-CDR mode.
Non-DPA Mode
Figure 8–18
and synchronizer blocks are disabled. Input serial data is registered at the rising or
falling edge of the serial LVDS_diffioclk clock produced by the left and right PLL.
You can select the rising/falling edge option using the ALTLDVS MegaWizard
Plug-In Manager software. Both data realignment and deserializer blocks are clocked
by the LVDS_diffioclk clock, which is generated by the left and right PLL.
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
Deserializer
Figure
DOUT DIN
shows the non-DPA datapath block diagram. In non-DPA mode, the DPA
8–17. The DPA and data realignment circuit cannot be used when the
IOE
2
Left/Right PLL
Left/Right PLL
3
DOUT DIN
Clock Mux
Bit Slip
(LVDS_LOAD_EN,
LVDS_diffioclk,
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
rx_outclk)
(Note
diffioclk
1), (2),
(3)
8 Serial LVDS
Clock Phases
Synchronizer
DOUT DIN
LVDS Receiver
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
February 2011 Altera Corporation
Retimed
DPA Circuitry
DPA Clock
Data
DIN
Differential Receiver
+
rx_in
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