XCS10XL-5TQ144C Xilinx Inc, XCS10XL-5TQ144C Datasheet - Page 31

• Manufacturer Part Number: XCS10XL-5TQ144C
• Description: IC FPGA 3.3V C-TEMP 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-XLr

Specifications of XCS10XL-5TQ144C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 112
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-LQFP
• Case: TQFP144
• Dc: 02+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Setting CCLK Frequency
In Master mode, CCLK can be generated in either of two
frequencies. In the default slow mode, the frequency ranges
from 0.5 MHz to 1.25 MHz for Spartan/XL devices. In fast
CCLK mode, the frequency ranges from 4 MHz to 10 MHz
for Spartan/XL devices. The frequency is changed to fast by
an option when running the bitstream generation software.
Data Stream Format
The data stream ("bitstream") format is identical for both
serial configuration modes, but different for the Spartan-XL
family Express mode. In Express mode, the device
becomes active when DONE goes High, therefore no length
count is required. Additionally, CRC error checking is not
supported in Express mode. The data stream format is
shown in
DS060 (v1.8) June 26, 2008
Product Specification
D0-D7
DOUT
CCLK
INIT
Table
R
16. Bit-serial data is read from left to right.
Notes:
1.
Symbol
T
T
T
T
F
If not driven by the preceding DOUT, CS1 must remain High until the
device is fully configured.
T
CCH
CCL
DC
CD
CC
IC
Figure 28: Express Mode Programming Switching Characteristics
T
IC
CCLK
T
DC
INIT (High) setup time
D0-D7 setup time
D0-D7 hold time
CCLK High time
CCLK Low time
CCLK Frequency
BYTE
0
Description
Header Received
BYTE
www.xilinx.com
1
Express mode data is shown with D0 at the left and D7 at
the right.
The configuration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones (or 24 fill bits, in Spartan-XL
family Express mode). This header is followed by the actual
configuration data in frames. The length and number of
frames depends on the device type (see
frame begins with a start field and ends with an error check.
In serial modes, a postamble code is required to signal the
end of data for a single device. In all cases, additional
start-up bytes of data are required to provide four clocks for
the startup sequence at the end of configuration. Long daisy
chains require additional startup bytes to shift the last data
through the chain. All start-up bytes are "don’t cares".
T
CD
Spartan and Spartan-XL FPGA Families Data Sheet
Min
20
45
45
BYTE
0
5
-
6
Max
10
-
-
-
-
-
Units
MHz
μs
ns
ns
ns
ns
FPGA Filled
DS060_28_080400
Table
17). Each
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