PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 15
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
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Chapter 6: Boot Module
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Chapter 7: PCI-XIO Module
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Chapter 8: General Purpose Input Output Pins
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PNX17XX_SER_1
Preliminary data sheet
Waveforms of the Blocking Logic
Clock Stretcher
Clock Detection Circuit
TM5250, DDR and QVCP clocks
QVCP_PROC Clock
QVCP_PIX Clock
Clock Dividers
Internal PNX17xx Series Clock from Dividers
Internal PNX17xx Series Clock from Dividers: PCI, SPDI, LCD and I2C
Internal PNX17xx Series Clock from Dividers: LCD Timestamp
GPIO Clocks
VDI_CLK1 Block Diagram
VDI_CLK2 Block Diagram
VDO_CLK1 Block Diagram
VDO_CLK2 Block Diagram
AO Clocks
AI Clocks
PHY LAN Clock Block Diagram
Receive and Transmit LAN Clocks
SPDO Clock
Boot Block Diagram
System Memory Map and Block Diagram Configuration for PNX17xx Series in Standalone Mode
System Memory Map and Block Diagram Configuration for PNX17xx Series in Host-assisted Mode
Document title variable Block Diagram
Read Status
Read Data
Write Data
Block Erase
Motorola Write With DSACK
Motorola Write Without DSACK
Motorola Read
NOR Flash Write
NOR Flash Read
IDE Interface
Isolation Translation Logic
Register Transfer/PIO Data Transfer on IDE
Timings on IDE Bus
IDE Transaction, Flow Controlled by Device IORDY
GPIO Module Block Diagram
Functional Block Diagram of a GPIO Pin
32-bit Timestamp Format
1-bit Signal Sampling
Up to 4-bit Signal Sampling
1-bit Pattern Generation
Up to 4-bit Samples per FIFO in Pattern Generation Mode
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Rev. 1 — 17 March 2006
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© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
. . . . 6-10
. . 6-13
-15
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