PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 532
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
2. Functional Description
PNX17XX_SER_1
Preliminary data sheet
Figure 1:
AI_OSCLK
Audio In Block Diagram
AI_SD[0]
AI_SCK
AI_SD[2]
AI_SD[3]
AI_SD[1]
AI_WS
Serial To Parallel Converter
SCK Divider
Clock Divider/Generator
WS Divider
The Audio In module has four major subsystems: a programmable sample clock
generator, a serial-to-parallel converter, a DTL initiator interface that initiates transfer
of parallel data to a DTL-to-memory bus adapter and a MMIO type low latency DTL
target interface for MMIO configuration registers.
The sampling clock can be used as either master or slave to the external A/D device.
The sampling clock synchronizes the serial-to-parallel converter with the source data
stream. The samples enter the serial-to-parallel converter, which reformats the data
for the initiator. The initiator streams the parallel data in to the DTL-to-memory bus
adapter. All the buffering of data is done in this adapter. The adapter also acts as the
DMA engine and bursts data to memory using the address provided by the initiator.
Since buffering of data is heavily dependent on system level latency issues, it is best
done in the adapter. Hence the buffer is not present in this block and instead will be in
the adapter and sized according to system requirements.
Serial
Clock
Shift Register
Shift Register
Shift Register
Shift Register
Different Framing/Capture Options
Rev. 1 — 17 March 2006
Divider Value
Divider Value
Parallel Data
MMIO Registers Logic
DTL DMA Interface Logic
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 16: Audio Input
16-2
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