PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 821
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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1. Introduction
2. Functional Description
The PNX17xx Series Device Control and Status (DCS) Network architecture is
designed to support the following:
The DCS bus is intended for MMIO traffic to configure the various modules in the
system. All modules can be accessed by the Boot module, and external PCI master
or the TM5250 itself. Access between the DCS bus and the memory is provided by
the DCS-Gate. This path is to be used by the boot module only!
page 3-30
bus.
A generic “Device Transaction Level” (DTL) point-to-point initiator-target
communication protocol is used on the boundary between a module and the DCS
bus. MMIO communication through the DTL protocol always consists of a single 32-
bit data element.
Each module on the DCS bus has a unique ID. The bus controller provides
programmable timeout generation with the following features:
The DCS network controllers generate selects for all the DCS targets according to
the address on the DCS network aperture map. See
Resources,
•
•
•
•
•
Chapter 30: DCS Network
PNX17xx Series Data Book – Volume 1 of 1
Rev. 1 — 17 March 2006
Separates MMIO traffic from DMA traffic:
–
Provides low latency access to modules:
–
Supports timeout generation.
Captures error and timeout information:
–
–
–
–
Allows interrupt generation for any non-masked timeouts and errors.
The TM5250 core has a high-performance, low-latency path to memory.
TM5250 ICache and DCache traffic is separated.
The TM5250 core has a low latency access to different modules of PNX17xx
Series system.
Initiator ID of the currently granted DCS Initiator
32-bit address of the currently granted DCS transaction
Encoded Target number for the currently selected DCS device
Additional information including read or write command information
in
Section 11. on page 3-31
Chapter 3 System On Chip Resources
for addresses of DCS target apertures.
pictures PNX17xx Series DCS
Chapter 3 System On Chip
Preliminary data sheet
Figure 3 on
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