CS42428-CQZ Cirrus Logic Inc, CS42428-CQZ Datasheet - Page 11

• Manufacturer Part Number: CS42428-CQZ
• Description: IC CODEC 8CH PLL 192KHZ 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42428-CQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 15
• Adc / Dac Resolution: 24bit
• Sampling Rate: 192kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1499 - BOARD EVAL FOR CS42428 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1031

DS605F1
SWITCHING CHARACTERISTICS
(For CQZ, T
VA = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, C
Notes:
RST Pin Low Pulse Width
PLL Clock Recovery Sample Rate Range
RMCK Output Jitter
RMCK Output Duty Cycle
OMCK Frequency
OMCK Duty Cycle
DAC_SCLK, ADC_SCLK Duty Cycle
DAC_LRCK, ADC_LRCK Duty Cycle
Master Mode
RMCK to DAC_SCLK, ADC_SCLK active edge delay
RMCK to DAC_LRCK, ADC_LRCK delay
Slave Mode
DAC_SCLK, ADC_SCLK Falling Edge to ADC_SDOUT,
ADC_SDOUT Output Valid
DAC_LRCK, ADC_LRCK Edge to MSB Valid
DAC_SDIN Setup Time Before DAC_SCLK Rising Edge
DAC_SDIN Hold Time After DAC_SCLK Rising Edge
DAC_SCLK, ADC_SCLK High Time
DAC_SCLK, ADC_SCLK Low Time
DAC_SCLK, ADC_SCLK falling to DAC_LRCK, SAI_LRCK
Edge
DAC_SCLK
ADC_SCLK
DAC_LRCK
ADC_LRCK
Figure 1. Serial Audio Port Master Mode Timing
(output)
(output)
RMCK
12. After powering-up the CS42428, RST should be held low after the power supplies and clocks are set-
13. See
14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.
15. Not valid when RMCK_DIV in
16. 76.5 ns for Single-Speed and Double-Speed modes, 23 ns for Quad-Speed Mode.
A
tled.
= -10 to +70° C; For DQZ, T
Table 1 on page 24
Parameters
t
smd
for suggested OMCK frequencies
t
lmd
A
“Clock Control (address 06h)” on page 48
= -40 to +85° C;
(Note 12)
(Note 14)
(Note 15)
(Note 13)
(Note 13)
Symbol
t
t
t
t
t
t
t
sckh
smd
t
lmd
dpd
lrpd
t
sckl
lrck
dh
ds
ADC_SDOUT
DAC_SDINx
DAC_LRCK
ADC_LRCK
DAC_SCLK
ADC_SCLK
Figure 2. Serial Audio Port Slave Mode Timing
(input)
(input)
1.024
Min
-25
30
45
40
45
45
10
30
20
20
1
0
0
-
t
lrckd
t
lrpd
t
lrcks
Typ
200
50
50
50
50
t
-
-
-
-
-
-
-
-
-
-
-
-
is set to Multiply by 2.
ds
M SB
t
sckh
t
dh
L
(Note 16)
25.600
= 30 pF)
Max
26.5
200
+25
55
60
55
55
15
15
-
-
-
-
-
-
t
sckl
t dpd
CS42428
MSB-1
ps RMS
Units
MHz
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
%
11