CS42428-CQZ Cirrus Logic Inc, CS42428-CQZ Datasheet - Page 31

• Manufacturer Part Number: CS42428-CQZ
• Description: IC CODEC 8CH PLL 192KHZ 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42428-CQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 15
• Adc / Dac Resolution: 24bit
• Sampling Rate: 192kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1499 - BOARD EVAL FOR CS42428 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1031

DS605F1
4.5.4
Functional Mode Register (addr = 03h)
Interface Format Register (addr = 04h)
Misc. Control Register (addr = 05h)
Set DAC_FMx = ADC_FMx = 00,01,10
Set ADC_CLK_SEL = 0
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00,01,10
Set DAC_OLx bits = 00,01,10
Set DAC_SP M/S = 1
Set ADC_SP M/S = 1
Set EXT ADC SCLK = 0
ADC Mode
4.5.4.1
One-Line Mode Configuration #1 can support up to 8 channels of DAC data, and 6 channels of ADC data.
This is the only configuration which will support up to 24-bit samples at a sampling frequency of 48 kHz on
all channels for both the DAC and ADC.
Register / Bit Settings
One-Line Mode (OLM) Configurations
Line Mode
Not One-
One-Line
One-Line
Mode #1
Mode #2
OLM Config #1
DAC_SCLK=64Fs
DAC_LRCK=SSM/DSM/QSM
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
CS5361
CS5361
SDO UT1
SDO UT2
SCLK
MCLK
Not One-Line Mode
LRCK
Figure 17. OLM Configuration #1
DAC_LRCK must equal ADC_LRCK; sample rate conversion not supported
RMCK
ADCIN1
ADCIN2
CS42428
Select ADC operating mode, see table below for valid combinations
Select DAC operating mode, see table below for valid combinations
Configure ADC_SDOUT to be clocked from the DAC_SP clocks.
Select the digital interface format when not in One-Line Mode
ADC_SDOUT
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
Identify external ADC clock source as SAI Serial Port.
ADC_SCLK
ADC_LRCK
DAC_LRCK
DAC_SCLK
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
Configure DAC Serial Port to Master Mode.
Configure ADC Serial Port to Master Mode.
One-Line Mode #1
64Fs
64Fs,128Fs, 256Fs
ADC Data
DAC Mode
not valid
Description
LRCK_PO RT2
SDOUT1_PO RT2
SDOUT2_PO RT2
SDOUT3_PO RT2
SDOUT4_PO RT2
M CLK
SCLK_PO RT1
LRCK_PO RT1
SDIN_PORT1
SCLK_PO RT2
DIGITAL AUDIO
PROCESSOR
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
One-Line Mode #2
not valid
not valid
CS42428
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