CS42428-CQZ Cirrus Logic Inc, CS42428-CQZ Datasheet - Page 55

• Manufacturer Part Number: CS42428-CQZ
• Description: IC CODEC 8CH PLL 192KHZ 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42428-CQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 15
• Adc / Dac Resolution: 24bit
• Sampling Rate: 192kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1499 - BOARD EVAL FOR CS42428 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1031

DS605F1
6.15
6.15.1 ADC LEFT CHANNEL GAIN (LGAINX)
6.16
6.16.1 ADC RIGHT CHANNEL GAIN (RGAINX)
6.17
6.17.1 SERIAL PORT SYNCHRONIZATION (SP_SYNC)
SP_SYNC
Reserved
Reserved
7
7
7
ADC Left Channel Gain (address 1Ch)
ADC Right Channel Gain (address 1Dh)
Interrupt Control (address 1Eh)
Default = 00h
Function:
Default = 00h
Function:
The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in
The level of the right analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in
Default = 0
0 - DAC & ADC Serial Port timings not in phase
1 - DAC & ADC Serial Port timings are in phase
Function:
Forces the LRCK and SCLK from the DAC & ADC Serial Ports to align and operate in phase. This
function will operate when both ports are running at the same sample rate or when operating at dif-
ferent sample rates.
Table
Table
Reserved
Reserved
Reserved
6
6
6
15.
15.
Binary Code
001010
000101
000000
110110
110001
001111
111011
DE-EMPH1
RGAIN5
LGAIN5
Table 15. Example ADC Input Gain Settings
5
5
5
DE-EMPH0
RGAIN4
LGAIN4
Decimal Value
4
4
4
+15
+10
-10
-15
+5
-5
0
RGAIN3
LGAIN3
INT1
3
3
3
Volume Setting
RGAIN2
LGAIN2
+15 dB
+10 dB
-10 dB
-15 dB
+5 dB
-5 dB
0 dB
INT0
2
2
2
Reserved
RGAIN1
LGAIN1
1
1
1
CS42428
Reserved
RGAIN0
LGAIN0
0
0
0
55