CS42428-CQZ Cirrus Logic Inc, CS42428-CQZ Datasheet - Page 47

• Manufacturer Part Number: CS42428-CQZ
• Description: IC CODEC 8CH PLL 192KHZ 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42428-CQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 15
• Adc / Dac Resolution: 24bit
• Sampling Rate: 192kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1499 - BOARD EVAL FOR CS42428 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1031

DS605F1
6.6.4
6.6.5
6.6.6
6.6.7
INTERPOLATION FILTER SELECT (FILT_SEL)
HIGH-PASS FILTER FREEZE (HPF_FREEZE)
DAC SERIAL PORT MASTER/SLAVE SELECT (DAC_SP M/S)
ADC SERIAL PORT MASTER/SLAVE SELECT (ADC_SP M/S)
Default = 0
Function:
Default = 0
Function:
Default = 0
Function:
Default = 0
Function:
This feature allows the user to select whether the DAC interpolation filter has a fast- or slow roll-off.
For filter characteristics, please See
0 - Fast roll-off.
1 - Slow roll-off.
When this bit is set, the internal high-pass filter for the selected channel will be disabled. The current
DC offset value will be frozen and continue to be subtracted from the conversion result. See
ital Filter Characteristics” on page
In Master Mode, DAC_SCLK and DAC_LRCK are outputs. Internal dividers will divide the master
clock to generate the serial clock and left/right clock. In Slave Mode, DAC_SCLK and DAC_LRCK
become inputs.
If the DAC_SP is in Slave Mode, DAC_LRCK must be present for proper device operation.
In Master Mode, ADC_SCLK and ADC_LRCK are outputs. Internal dividers will divide the master
clock to generate the serial clock and left/right clock. In Slave Mode, ADC_SCLK and ADC_LRCK
become inputs.
If the ADC_SP is in Slave Mode, ADC_LRCK must be present for proper device operation.
To use the PLL to lock to ADC_LRCK, the ADC_SP must be in Slave Mode. When using the PLL to
lock to LRCK, if ADC_SDOUT is configured to be clocked by the ADC_SP, both ADC_SCLK and
ADC_LRCK must be present. If ADC_SDOUT is configured to be clocked by the DAC_SP, only the
ADC_LRCK signal must be applied.
8.
“D/A Digital Filter Characteristics” on page
10.
CS42428
“A/D Dig-
47