CS42428-CQZ Cirrus Logic Inc, CS42428-CQZ Datasheet - Page 33

• Manufacturer Part Number: CS42428-CQZ
• Description: IC CODEC 8CH PLL 192KHZ 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42428-CQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 15
• Adc / Dac Resolution: 24bit
• Sampling Rate: 192kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1499 - BOARD EVAL FOR CS42428 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1031

DS605F1
Functional Mode Register (addr = 03h)
Interface Format Register (addr = 04h)
Misc. Control Register (addr = 05h)
ADC Mode
Set DAC_FMx = 00,01,10
Set ADC_FMx = 00,01,10
Set ADC_CLK_SEL = 1
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00,01
Set DAC_OLx bits = 00,01,10
Set DAC_SP M/S = 1
Set ADC_SP M/S = 0 or 1
Set EXT ADC SCLK = 0
4.5.4.3
This configuration will support up to 8 channels of DAC data and 6 channels of ADC data. OLM Config #3
will handle up to 20-bit ADC samples at an Fs of 48 kHz and 24-bit DAC samples at an Fs of 48 kHz. Since
the ADC’s data stream is configured to use the ADC_SDOUT output and the internal and external ADCs
are clocked from the ADC_SP, the sample rate for the DAC Serial Port can be different from the sample
rate of the ADC serial port.
Register / Bit Settings
Line Mode
One-Line
One-Line
Not One-
Mode #1
Mode #2
OLM Config #3
DAC_SCLK=64Fs
DAC_LRCK=SSM/DSM/QSM
ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM
DAC_SCLK=64Fs
DAC_LRCK=SSM/DSM/QSM
ADC_SCLK=128Fs
ADC_LRCK=SSM
CS5361
CS5361
Not One-Line Mode
SDOUT1
SDOUT2
SCLK
LRCK
MCLK
not valid
Figure 19. OLM Configuration #3
RMCK
ADCIN1
ADCIN2
CS42428
DAC_LRCK can run at SSM, DSM, or QSM independent of ADC_LRCK
ADC_LRCK can run at SSM, DSM, or QSM independent of DAC_LRCK
Select ADC operating mode, see table below for valid combinations
Select DAC operating mode, see table below for valid combinations
Configure ADC_SDOUT to be clocked from the ADC_SP clocks.
Select the digital interface format when not in One-Line Mode
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=128Fs
ADC_LRCK=SSM
ADC_SDOUT
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
DAC_SCLK
DAC_LRCK
ADC_SCLK
ADC_LRCK
Identify external ADC clock source as ADC Serial Port.
Set ADC Serial Port to Master Mode or Slave Mode.
One-Line Mode #1
DAC Mode
Set DAC Serial Port to Master Mode.
64Fs,128Fs,256Fs
not valid
64Fs,128Fs
Description
SDIN_PORT1
MCLK
SCLK_PORT1
LRCK_PORT1
LRCK_PORT2
SDOUT1_PORT2
SDOUT2_PORT2
SDOUT3_PORT2
SDOUT4_PORT2
SCLK_PORT2
DIGITAL AUDIO
PROCESSOR
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=128Fs
ADC_LRCK=SSM
One-Line Mode #2
not valid
CS42428
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