CS42428-CQZ Cirrus Logic Inc, CS42428-CQZ Datasheet - Page 23

• Manufacturer Part Number: CS42428-CQZ
• Description: IC CODEC 8CH PLL 192KHZ 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42428-CQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 15
• Adc / Dac Resolution: 24bit
• Sampling Rate: 192kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1499 - BOARD EVAL FOR CS42428 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1031

DS605F1
4.4
4.4.1
Clock Generation
The clock generation for the CS42428 is shown in the figure below. The internal MCLK is derived from the
output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the
SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL
lock to the other source input.
OMCK
PLL and Jitter Attenuation
The PLL can be configured to lock onto the incoming ADC_LRCK signal from the ADC Serial Port and
generate the required internal master clock frequency. There are some applications where low jitter in the
recovered clock, presented on the RMCK pin, is important. For this reason, the PLL has been designed
to have good jitter-attenuation characteristics. By setting the PLL_LRCK bit to a ‘1’ in the register
Control (address 06h)” on page
master clock (RMCK) of 256Fs.
ADC_LRCK.
See
components, optimal layout guidelines, and jitter-attenuation characteristics.
“Appendix B: PLL Filter” on page 62
(slave mode)
PLL_LRCK bit
ADC_LRCK
PLL (256Fs)
49.152 MHz
8.192 -
Internal
00
01
48, the PLL will lock to the incoming ADC_LRCK and generate an output
MCLK
Figure 10. Clock Generation
Table 2
(manual or auto
SW _CTRLx bits
switch)
Auto Detect
Input Clock
X2
1,1.5, 2, 4
shows the output of the PLL with typical input Fs values for
for more information concerning PLL operation, required filter
2
4
00
01
10
11
RMCK_DIVx bits
double
double
single
speed
speed
speed
single
speed
speed
speed
quad
quad
256
128
64
4
2
1
ADC_FMx bits
00
01
10
00
01
10
00
01
10
00
01
10
DAC_FMx bits
128FS
256FS
128FS
256FS
ADC_SP SELx bits
or ADC_OLx bits
not OLM
not OLM
OLM #1
OLM #1
OLM #2
OLM #2
ADC_OLx and
DAC_OLx
RMCK
DAC_LRCK
DAC_SCLK
ADC_LRCK
ADC_SCLK
CS42428
“Clock
23