CS42428-CQZ Cirrus Logic Inc, CS42428-CQZ Datasheet - Page 12

IC CODEC 8CH PLL 192KHZ 64-LQFP

CS42428-CQZ

Manufacturer Part Number
CS42428-CQZ
Description
IC CODEC 8CH PLL 192KHZ 64-LQFP
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet

Specifications of CS42428-CQZ

Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 8
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
114 / 114
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
8
No. Of Input Channels
2
No. Of Output Channels
15
Adc / Dac Resolution
24bit
Sampling Rate
192kSPS
Ic Interface Type
I2C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1499 - BOARD EVAL FOR CS42428 CODEC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1031

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS42428-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
135
Part Number:
CS42428-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS42428-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
12
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(For CQZ, T
Inputs: Logic 0 = DGND, Logic 1 = VLC, C
Notes:
SCL Clock Frequency
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
R S T
S D A
S C L
17. Data must be held for sufficient time to bridge the transition time, t
18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
19.
A
-------------------- -
256
Stop
= -10 to +70° C; For DQZ, T
t
15
t
irs
×
buf
Fs
for Single-Speed Mode,
Sta rt
Parameter
t
t
hdst
lo w
t
hdd
Figure 3. Control Port Timing - I²C Format
t
A
L
high
= -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V;
= 30 pF)
-------------------- -
128 Fs
t sud
15
×
(Note 17)
(Note 18)
t ack
for Double-Speed Mode,
Symbol
t
t
t
t
t
t
t
t
t
susp
f
hdst
high
sust
t
hdd
low
sud
t
t
ack
buf
scl
irs
rc
fc
R e p e ate d
t sust
Sta rt
fc
, of SCL.
Min
500
250
4.7
4.0
4.7
4.0
4.7
4.7
0
-
-
-
-
t
hdst
----------------- -
64 Fs
t rd
15
×
t rc
for Quad-Speed Mode
(Note 19)
t fc
Max
100
300
1
-
-
-
-
-
-
-
-
-
t fd
CS42428
Stop
DS605F1
t susp
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns

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