LAN9311-NU SMSC, LAN9311-NU Datasheet - Page 143

• Manufacturer Part Number: LAN9311-NU
• Description: IC ETHER SW 2PRT 16BIT 128-VTQFP
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9311-NU

• Controller Type: Ethernet Switch Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1076 - EVALUATION BOARD LAN9311-NU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1075

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
10.2.2.3
10.2.2.4
A
C
K
S 1 0 1 0
C
C
A
K
A
K
Control Byte
Chip / Block
Select Bits
S 1 0 1 0
S 1 0 1 0
I
Following the device addressing, a data byte may be read from the EEPROM by outputting a start
condition and control byte with a control code of 1010b, chip/block select bits as described in
Section
8-bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and
the EPC_TIMEOUT bit in the
sends a no-acknowledge, followed by a stop condition.
Figure 10.4
For a register level description of a read operation, refer to
Operation," on page
I
Following the device addressing, data bytes may be read sequentially from the EEPROM by outputting
a start condition and control byte with a control code of 1010b, chip/block select bits as described in
Section
8-bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and
the EPC_TIMEOUT bit in the
sends an acknowledge, and the EEPROM responds with the next 8-bits of data. This continues until
the last desired byte is read, at which point the I
stop condition.
Figure 10.4
addressing.
Single Byte Addressing Read
2
2
C EEPROM Byte Read
C EEPROM Sequential Byte Reads
A
1
0
Control Byte
Control Byte
Chip / Block
Chip / Block
A
9
Select Bits
Select Bits
10.2.2.2, and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by
10.2.2.2, and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by
A
8
A
1
0
0 0 0
1
R/~W
illustrates typical I
A
9
illustrates typical I
A
C
K
A
8
D
7
1
1
Figure 10.5 I
R/~W
R/~W
D
6
A
C
K
A
C
K
139.
Data Byte
D
5
D
D
7
7
D
4
Figure 10.4 I
D
6
D
6
Double Byte Addressing Sequential Reads
Single Byte Addressing Sequential Reads
D
3
Data Byte
Data Byte
D
5
D
5
D
2
D
D
4
4
2
EEPROM Command Register (E2P_CMD)
EEPROM Command Register (E2P_CMD)
C EEPROM byte read for single and double byte addressing.
2
D
D
3
D
3
1
C EEPROM Sequential Byte Reads
2
C EEPROM sequential byte reads for single and double byte
D
D
2
2
D
0
DATASHEET
D
D
1
1
A
C
K
2
C EEPROM Byte Read
D
0
D
0
P
A
C
K
A
C
K
143
D
7
D
7
D
6
D
6
A
C
K
Data Byte
Data Byte
D
D
5
5
S 1 0 1 0
2
D
D
4
4
C master sends a no-acknowledge, followed by a
D
3
D
3
D
2
D
2
Control Byte
Chip / Block
Select Bits
D
1
D
1
Double Byte Addressing Read
D
0
D
0
0 0 0
A
C
K
A
C
K
Section 10.2.1, "EEPROM Controller
...
...
D
7
D
7
1
R/~W
D
D
6
6
A
C
K
Data Byte
Data Byte
D
5
D
5
is set. The I
is set. The I
D
7
D
4
D
4
D
6
D
D
3
3
Data Byte
D
5
D
2
D
2
Revision 1.7 (06-29-10)
D
D
D
1
1
4
D
D
0
0
D
3
2
2
C master then
C master then
A
C
K
A
C
K
D
2
P
P
D
1
D
0
A
C
K
P