LAN9311-NU SMSC, LAN9311-NU Datasheet - Page 196

• Manufacturer Part Number: LAN9311-NU
• Description: IC ETHER SW 2PRT 16BIT 128-VTQFP
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9311-NU

• Controller Type: Ethernet Switch Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1076 - EVALUATION BOARD LAN9311-NU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1075

Revision 1.7 (06-29-10)
14.2.3.3
31:28
27:16
15:12
BITS
11:0
RESERVED
GPIO Interrupt Enable[11:0] (GPIO[11:0]_INT_EN)
When set, these bits enable the corresponding GPIO interrupt.
Note:
RESERVED
GPIO Interrupt[11:0] (GPIO[11:0]_INT)
These signals reflect the interrupt status as generated by the GPIOs. These
interrupts are configured through the
Register
Note:
General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
This read/write register contains the GPIO interrupt status bits.
Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these
interrupt bits are cascaded into bit 12 (GPIO) of the
to any of the interrupt enable bits will enable the corresponding interrupt as a source. Status bits will
still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt
in this register. Bit 12 (GPIO_EN) of the
for an actual system level interrupt to occur. Refer to
additional information.
The GPIO interrupts must also be enabled via bit 12 (GPIO_EN) of
the
interrupt pin (IRQ) to be asserted.
(GPIO_CFG).
As GPIO interrupts, GPIO inputs are level sensitive and must be
active greater than 40 nS to be recognized as interrupt inputs.
Offset:
Interrupt Enable Register (INT_EN)
1E8h
DESCRIPTION
General Purpose I/O Configuration
DATASHEET
Interrupt Enable Register (INT_EN)
196
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
in order to cause the
Size:
Interrupt Status Register
Chapter 5, "System Interrupts," on page 49
32 bits
must also be set in order
TYPE
R/WC
R/W
SMSC LAN9311/LAN9311i
RO
RO
(INT_STS). Writing a 1
DEFAULT
Datasheet
0h
0h
-
-
for