LAN9311-NU SMSC, LAN9311-NU Datasheet - Page 322
LAN9311-NU
Manufacturer Part Number
LAN9311-NU
Description
IC ETHER SW 2PRT 16BIT 128-VTQFP
Manufacturer
SMSC
Type
Two Port Managed Ethernet Switchr
Specifications of LAN9311-NU
Controller Type
Ethernet Switch Controller
Interface
Serial EEPROM
Voltage - Supply
3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Product
Ethernet Switches
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 MB, 100 MB
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Maximum Operating Temperature
+ 70 C
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
For Use With
638-1076 - EVALUATION BOARD LAN9311-NU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1075
Available stocks
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Quantity
Price
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Manufacturer:
CINCERA
Quantity:
3 023
Company:
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LAN9311-NU
Manufacturer:
Microchip Technology
Quantity:
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Part Number:
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Quantity:
20 000
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Revision 1.7 (06-29-10)
14.5.1.3
BITS
31:9
8:7
4:3
6
5
2
1
0
RESERVED
RESERVED
Note:
Buffer Manager Interrupt Mask (BM)
When set, prevents the generation of switch fabric interrupts due to the
Buffer Manager via the
(BM_IPR). The status bits in the SW_IPR register are not affected.
Switch Engine Interrupt Mask (SWE)
When set, prevents the generation of switch fabric interrupts due to the
Switch Engine via the
The status bits in the SW_IPR register are not affected.
RESERVED
Note:
Port 2 MAC Interrupt Mask (MAC_2)
When set, prevents the generation of switch fabric interrupts due to the Port
2 MAC via the MAC_IPR_2 register (see
The status bits in the SW_IPR register are not affected.
Port 1 MAC Interrupt Mask (MAC_1)
When set, prevents the generation of switch fabric interrupts due to the Port
1 MAC via the MAC_IPR_1 register (see
The status bits in the SW_IPR register are not affected.
Port 0 MAC Interrupt Mask (MAC_MII)
When set, prevents the generation of switch fabric interrupts due to the Port
0 MAC via the MAC_IPR_MII register (see
The status bits in the SW_IPR register are not affected.
Switch Global Interrupt Mask Register (SW_IMR)
This read/write register contains the global interrupt mask for the switch fabric interrupts. All switch
related interrupts in the
register. An interrupt is masked by setting the corresponding bit of this register. Clearing a bit will
unmask the interrupt. When an unmasked switch fabric interrupt is generated in the
Interrupt Pending Register
Status Register
These bits must be written as 11b
These bits must be written as 11b
Register #:
(INT_STS). Refer to
Switch Engine Interrupt Pending Register
Buffer Manager Interrupt Pending Register
Switch Global Interrupt Pending Register (SW_IPR)
0004h
DESCRIPTION
(SW_IPR), the interrupt will trigger the SWITCH_INT bit in the
DATASHEET
Chapter 5, "System Interrupts," on page 49
Section 14.5.2.44, on page
Section 14.5.2.44, on page
Section 14.5.2.44, on page
322
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Size:
(SWE_IPR).
32 bits
367).
367).
367).
TYPE
may be masked via this
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMSC LAN9311/LAN9311i
RO
for more information.
Switch Global
DEFAULT
11b
11b
Datasheet
1b
1b
1b
1b
1b
Interrupt
-
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